Signal Integrity Webcasts
 |
 |
|
Techniques for Successful High-Speed Design |
|
Altera’s signal integrity webcasts provide the detailed information you need to make your next high-speed design successful. Topics include effective design techniques to mitigate SSN, implementing the latest DDR3 interfaces, and more. All webcasts are available on-demand and can be viewed at any time.
|
 Implementing High-Speed DDR3 Interfaces 
With today’s requirements for high-speed memory interfaces surpassing 1 Gbps, FPGA silicon and IP must be designed to provide robust signal integrity and address the challenges of implementing DDR3 interfaces. Simulation still plays an important role in validating signal levels and timing margins. This webcast will discuss the challenges of implementing DDR3 as well as available solutions. View Now
|
|
Signal & Power Integrity Design Techniques for SSN
This webcast teaches signal integrity design techniques to mitigate SSN, including how to maintain power integrity. You’ll learn about measurement criteria, measured results, and data on design prototypes and simulation predictions. View Now
|
|
Plug & Play Signal Integrity
Altera’s Stratix® II GX family of FPGAs, with Plug & Play Signal Integrity technology, help deliver the best system BER performance and allow you to design truly universal cards that can plug into multiple slots in a high-speed backplane system. This webcast will review high-speed protocol trends as well as the challenges facing high-speed backplane designers. We’ll conclude with a short video about how Altera’s Plug & Play Signal Integrity can help you with your backplane designs using multi-gigabit transceivers. View Now
|
|
Gigabit Channel Design Guidelines
Though high-speed serial links increase data throughput and reduce the number of traces on a board, a different set of challenges arise when designing these systems. This seminar provides useful guidelines and techniques when designing a high-speed channel. The seminar will cover a channel model case study that includes how to address the challenges of designing at high data rates (BGA breakout, crosstalk, vias, DC block capacitor, and an SMA connector). These challenges are tied in and are implemented in a complete end-to-end channel simulation. View Now
|
|
Learn About High-Speed Clocking Architecture and Oscillator Selection for FPGAs
In high-speed or wide-bus interfaces, such as gigabit transceiver or high-speed memory interfaces, room for clock uncertainties and variations is small. Unfortunately, we live in a world where clock oscillators do have frequency variations and are exposed to jitter. This net seminar covers various clock network topologies for FPGAs as well as a detailed discussion of jitter, its components and causes. Finally, guidelines are provided for how to select the right oscillator for your high speed design. View Now
|
|
Learn Power Delivery Network (PDN) Best Design Practices for High-Speed Boards
The power delivery network (PDN) is a critical design component in board designs, especially for high-speed systems. A robust PDN is required to achieve a high level of system signal integrity. In this net seminar, the SI Doctor, Dr. Eric Bogatin, provides detailed practical strategies for achieving low PDN impedance. Dr. Bogatin covers voltage regulator modeling and simulations and techniques to estimate and achieve PDN target impedance. He also provides a close look at profiles and the proper selection of decoupling capacitors.
View Now
|
|
Literature
> 
