Demo Video: Interfacing 1,067-Mbps DDR3 Memory to Stratix III FPGAs
High-speed DDR3 memory design can be challenging because DDR3 introduces deliberately staggered data at higher frequencies. Without leveling built directly into an FPGA I/O structure, connecting to a DDR3 SDRAM DIMM is costly, time-consuming, and requires additional components that consume precious board space.
Stratix® III FPGAs, with their proprietary built-in I/O circuitry, reduce the challenges of high-speed DDR3 memory design. Watch this demo to see how easy it is to interface 1,067 Mbps DDR3 memories to Stratix III FPGAs.
Stratix III FPGAs:
- Feature robust DDR3 write-leveling for interfacing with high-speed DDR3 memory
- Provide I/O circuitry that is capable of high speeds and greater flexibility to support existing and emerging external memory standards
- Maintain optimal signal integrity at high data rates
Get Started with Your DDR3 Memory Design
For in-depth technical information on the DDR3 memory interfacing capabilities of Stratix III FPGAs:
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