Altera was founded in 1983 by Robert Hartmann, Michael Magranet, Paul Newhagen, and Jim Sansbury, visionaries who capitalized on the research of the day. They believed that semiconductor customers would benefit from a user-programmable standard product alternative to gate arrays. To address these market needs, Altera's founders pioneered the first reprogrammable logic device, the EP300, giving birth to an entirely new market segment in semiconductors. This new, flexible solution beat traditional standard products to market and launched Altera's reputation as a semiconductor innovation leader.
1983 1984 1985 1988 1991 1992 1993 1994 1995 1996 1997 1998 1999 2000 2001 2002 2003 2004 2005 2006
2007 2008 2009 2010 2011
Table 1 lists major industry innovations in Altera® programmable solutions.
Table 1. Programmable Logic Device (PLD) Industry Innovation Firsts
| Year | Technology Milestones | PLD Industry Innovation Firsts |
|---|---|---|
| 2011 | OpenCL Program | Announces the industry's first development program focused on the Open Computing Language (OpenCL™) standard for FPGAs and SoC FPGAs. OpenCL program combines the parallel performance capability of FPGAs with the OpenCL standard to enable system acceleration. |
| 2011 | ARM-based SoC FPGAs | Integrates a dual-core ARM® Cortex™-A9 MPCore™ hard processor system (HPS) that includes processors, peripherals, and a 100-Gbps high-performance interconnect into the fabric of a 28-nm Low-Power (28LP) FPGA. |
| 2011 | Direct optical interfaces | Direct optical interfaces in programmable devices will provide substantially increased network bandwidth and port density, along with lower system complexity, cost, and power. |
| 2011 | 28-nm device portfolio | Four device families – new Cyclone® V FPGAs, new Arria® V FPGAs, enhanced Stratix® V FPGAs, and HardCopy® V ASICs – comprise a portfolio that is tailored to your diverse design needs. Enables you to differentiate your products without sacrificing any performance, power, or cost. |
| 2011 | Cyclone V FPGAs | Industry's lowest system cost and power FPGAs, with performance levels ideal for differentiating high-volume applications. |
| 2011 | Arria V FPGAs | Balances cost and power with performance for mid-range applications. |
| 2010 | MAX® V CPLDs | Uses half the total power versus competitive CPLDs, while providing lower total system cost and robust features including digital phase-locked loops (DPLLs). |
| 2010 | Arria II GX and GZ FPGAs | Enhanced with 6.375-Gbps transceivers and up to 1.25-Gbps LVDS support, and new GZ variant for higher bandwidth designs. |
| 2010 | Quartus® II software | 2X to 3X faster compile times versus the nearest competitor for high-density designs, new Transceiver Toolkit, and new Qsys system integration tool (in beta). |
| 2010 | Stratix V FPGAs | Industry's highest bandwidth FPGA, and Altera's first 28-nm devices. Offers up to 1.1 million logic elements (LEs), the industry's highest level of application-targeted intellectual property (IP) cores, and integrated transceivers at data rates up to 28 Gbps. |
| 2009 | Cyclone III LS FPGAs | Industry's first suite of security features at the silicon, software, and IP level on a low-power, high-functionality FPGA. This suite of security features protects your IP from tampering, reverse engineering, and cloning. |
| 2009 | Arria II GX FPGAs | Industry’s lowest power, cost-optimized 40-nm FPGAs with 3.75-Gbps transceivers, offering improvements in usability that enable designers to complete their projects faster. |
| 2009 | Stratix IV GT FPGAs | Industry’s only FPGAs with integrated 11.3-Gbps transceivers, ideal for 40G/100G applications. |
| 2008 | Stratix IV FPGAs | Industry's first 40-nm FPGAs, with highest density, highest performance, lowest power, highest transceiver bandwidth (up to 8.5-Gbps transceivers), and hard IP blocks for PCI Express® Gen1 and Gen2. |
| 2008 | Industry's first 40-nm HardCopy ASIC includes a 6.5+-Gbps transceivers option. | |
| 2007 | Arria GX FPGAs | Industry's first low-cost, transceiver-based, and protocol-optimized FPGAs. |
| 2007 | Cyclone III FPGAs | Industry's first low-cost 65-nm FPGA featuring an unprecedented combination of low power, high functionality, and low cost. |
| 2006 | Stratix III FPGAs | 65-nm FPGAs featuring support for increased levels of integration and complexity with higher densities and performance. |
| 2006 | Quartus II software | Native support for SDC design constraints. |
| 2006 | Nios® II C2H Acceleration Compiler | First automated ANSI C to register transfer level (RTL) generation tool for embedded processors. |
| 2006 | Stratix II GX FPGAs | Fastest and highest-density 90-nm FPGA fabric with up to 20 low-power transceivers that operate between 622 Mbps to 6.375 Gbps. |
| 2005 | HardCopy II ASICs | Fine-grained architecture; seamless migration from the 90-nm Stratix II FPGA prototype. |
| 2005 | Cyclone II FPGAs | 90-nm FPGAs featuring 30 percent lower cost and three times the density of the industry’s first low-cost FPGA. |
| 2004 | Stratix II FPGAs | 90-nm FPGAs in which 8-input "fracturable" look-up table (LUT) called an adaptive logic module (ALM) replaced the 4-input LUT architecture. |
| 2004 | Nios II embedded processor | World's most versatile embedded processor. |
| 2003 | Quartus II software | Programmable logic software package offers Tcl scripting support. |
| 2003 | Stratix GX FPGAs | 0.13-µm FPGAs with quad transceiver architecture. |
| 2003 | HardCopy Stratix ASICs | Industry’s only complete prototype-to-volume-production 0.13-µm solution. |
| 2003 | Stratix FPGAs | 0.13-µm, 300-mm, high-speed, high-density FPGAs. |
| 2002 | Quartus II software | Programmable logic design toolset offers Linux support. |
| 2002 | Cyclone FPGAs | World's lowest-cost FPGA (0.13 µm). |
| 2002 | SOPC Builder | First FPGA automated system generation tool. |
| 2002 | Stratix FPGAs | World's first FPGA with embedded DSP blocks. |
| 2001 | HardCopy APEXTM ASICs | The first seamless FPGA migration to low-cost HardCopy ASIC. |
| 2001 | System interconnect fabric | First automatically generated interconnect fabric that supports simultaneous master/slave transactions. |
| 2001 | Quartus II software | Quartus II design software introduced. |
| 2001 | MercuryTM FPGAs | World's first 0.18-µm FPGA with embedded transceivers. |
| 2000 | ARM-based ExcaliburTM devices | World's first FPGA with hard embedded processor. |
| 2000 | Nios embedded processors | World's first embedded processor optimized for programmable logic. |
| 1999 | Intellectual property (IP) | Altera's IP MegaStoreTM website launched. |
| 1999 | APEX EP20K1500E FPGAs | Industry's first PLD with more than 1.5 million gates. |
| 1999 | Quartus software | Embedded logic analyzer (SignalTapTM logic analyzer). |
| 1998 | Quartus software | Support for encrypted IP cores. |
| 1997 | Quartus software | GUI to configure parameterized modules and IP cores (MegaWizard® Plug-In Manager). |
| 1996 | FLEX® 10KA FPGAs | FPGA with integrated phase-locked loop (PLL). |
| 1995 | FLEX 10K FPGAs | FPGA with embedded block RAM. |
| 1994 | MAX 9000 CPLDs | JTAG in-system reprogrammable CPLD. |
| 1993 | Quartus software | Support for library of parameterized modules (LPM). |
| 1992 | FLEX 8000 FPGAs | Altera's first FPGA. |
| 1991 | MAX+PLUS® II software | Windows-based logic design toolset. |
| 1988 | MAX+PLUS II software | Full-featured integrated graphical CAD environment for logic design. |
| 1988 | MAX 5000 CPLDs | World's first high-density CPLD. Patented redundancy technology delivers reduction of defects and increased yields (first introduced in 0.65 µm, this key technology continues to deliver increased yields in Altera 65-nm devices today). |
| 1985 | EP1200 | Industry's first high-density CMOS PLD. |
| 1984 | A+PLUS software | Industry's first PC-based development system. |
| 1984 | EP300 device and die | World's first reprogrammable logic device. |
| 1983 | Demonstration box | Altera's first demonstration box, "T-bird Tail Lights". |
| 1983 | - | Altera Corporation founded. |
