Altera Ships Highest Density, Highest System-Bandwidth FPGA Targeting 40G/100G Applications

Stratix IV GT FPGAs Deliver 530K Logic Elements and Integrated 11.3-Gbps Transceivers

San Jose, Calif., June 1, 2009—Altera Corporation (NASDAQ: ALTR) today announced availability of the industry's highest density, highest system-bandwidth FPGA to address the stringent demands of today's bandwidth-heavy applications. Featuring 11.3-Gbps transceivers and 530K logic elements (LEs), the Stratix^® IV GT EP4S40G5 and EP4S100G5 FPGAs are the latest variants of Altera's 40-nm Stratix IV FPGA family shipping to customers. Stratix IV GT FPGAs support next-generation 40G/100G technologies, including 40/100 Gigabit Ethernet (GbE) media access controllers (MACs), optical transport network (OTN) framers and mappers, 40G/100G Enhanced Forward Error Correction (EFEC) solutions, and 10G chip-to-chip and chip-to-module bridging applications used in communications systems, high-end test equipment and military communications systems.

“From a test perspective, building the 100G ecosystem requires reliable functionality from the physical layer upwards. The breadth and depth of 100G applications demands silicon solutions that offer sophisticated and deep functionality, high performance and density,” said Jerry Gentile, senior vice president in JDSU's communications test and measurement business segment. “Supported by Altera's Stratix IV GT FPGAs, JDSU test solutions are ready for the comprehensive testing and validation of high-end communication systems with the ability to scale up to the latest communication solutions.”

Stratix IV GT devices are the only FPGAs that offer a single-chip solution featuring 11.3-Gbps integrated transceivers that can interface directly to a CFP optical module and meet the emerging IEEE 802.3ba standard for 100G MACs. The unprecedented density and bandwidth in Stratix IV GT FPGAs provide designers of 40G/100G applications the flexibility to incorporate traffic management, packet processing and their own custom functionality into a single device.

Stratix IV GT FPGAs deliver breakthrough levels of system bandwidth and power efficiency for high-bandwidth applications. Stratix IV GT devices feature up to 48 integrated transceivers, a low 0.9V core power supply, on-die and on-packing decoupling, 20.7 Mbits of embedded memory, 1,024 18x18 multipliers and up to 530K LEs. The devices support a wide variety of protocols and standards, including SFI-S, SFI-5.1, SFI-5.2, MLD, Interlaken, CEI-6G/11G, CAUI, XLAUI and feature hard IP for PCIe Gen1 and Gen2 (x1, x4, x8).

“The increased usage of broadband content like HDTV and Internet video is placing tremendous strains on older networks that were not designed to manage the amount of traffic these applications generate,“ said Luanne Schirrmeister, senior director of component product marketing, Altera Corporation. “This is forcing the telecommunications industry to ramp up their 40G/100G networks as quickly as possible. With Stratix IV GT FPGAs, we deliver a single-chip solution that is specifically optimized to address the high-speed data-rate and bandwidth requirements of this emerging market.”

Stratix IV GT FPGA Availability

The Stratix IV GT EP4S40G5 and EP4S100G5 devices are currently shipping, with other family members scheduled to ship in 2009. For more information on Stratix IV GT FPGAs and how the devices can support 40G/100G applications, contact your local Altera sales representative or visit http://www.altera.com/pr/stratixIV-transceivers. To view a white paper that highlights how Altera's FPGAs enable 40G/100G applications, visit http://www.altera.com/pr/40-100G-wp.

About Altera

Altera programmable solutions enable system and semiconductor companies to rapidly and cost-effectively innovate, differentiate and win in their markets. Find out more about Altera's FPGA, CPLD and ASIC devices at www.altera.com. To subscribe to Altera's RSS/XML news feeds, visit Altera RSS Feeds.

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