For Release: April 09, 2008
***MEDIA ALERT***
Altera Showcases Low-Power Solutions at ESC 2008
San Jose, Calif., April 9, 2008¾
What:
Altera Corporation (NASDAQ: ALTR) will showcase its industry-leading low-power embedded technologies and programmable logic at the 2008 Embedded Systems Conference (ESC) Silicon Valley. Through sponsored tracks and in-booth demonstrations, attendees will learn how to rapidly reduce the power consumption and increase the flexibility of their embedded designs. The combination of the Nios® II embedded processor, the industry’s most widely used soft processor, and Altera’s latest portfolio of low-power FPGAs and easy-to-use development tools, offers embedded designers a powerful competitive edge.
Come see live demonstrations and presentations at booth 2034. In addition, Altera will be conducting 90-minute sponsored sessions in McEnery-Room L on the following topics:
Intelligent Power Management of FPGA Designs—Presented by Steven Kravatsky
Tuesday, April 15, 2008, 8:30 am–10:00 am and 2:30 pm–4:00 pm
This session shows you how to create embedded systems using solutions from Altera and Linear Technology that are power efficient and run off batteries. Learn how to dynamically modify FPGA power utilization using intelligent power management.
Designing Embedded Systems With FPGAs—Presented by Rodney Frazer
Tuesday, April 15, 2008, 10:30 am–12:00 pm and 4:30 pm–6:00 pm
This session shows you how to create embedded systems implemented in programmable logic. Learn how to build a processor-based hardware system and run software on it. See how quick and easy it is to build entire systems using Altera’s SOPC Builder tool to configure and integrate hardware intellectual property (IP) blocks.
Product and Solution Demonstrations
- Low power
- Reduce power consumption by adding hardware accelerators with the Nios II C2H Compiler
- Intelligent power management with the Low Power Reference Platform
- Hardware design
- SOC development with FPGAs with SOPC Builder
- Flexible hardware debug with FPGAs using SignalTap II
- Zero-power Max®IIZ CPLD
- Hardware acceleration in COTS systems with XtremeData
- ARM Cortex-M1
- Software development
- Nios II Embedded Design Suite (EDS)
- uCLinux on the Nios II processor
- New to FPGA design
- Build your first FPGA design
When: April 14–18, 2008
Where: Booth 2034 and Room L
McEnery Covention Center
San Jose, CA
For additional information, visit www.altera.com/education/events/northamerica/evt-esc-2008.html.
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