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For Release: December 6, 1999
Altera Ships Two New Parameterizable UTOPIA Level 2 Communication Cores
- Optimized for FLEX® 10KE and APEX™ PLDs at Speeds Over
80 MHz
- Compliant With ATM Forum UTOPIA Level 2, Version 1.0 Specification
- Fully Parameterizable with MegaWizard™ Plug-In and OpenCore™
Evaluation Support
San Jose, Calif., December 6, 1999-- Altera Corporation (Nasdaq: ALTR) today
announced that it is shipping two new UTOPIA (Universal Test and Operation PHY
Interfaces for ATM) cores, including a Level 2 Master and a Level 2 Slave. Both
cores were developed internally through its MegaCore program and are optimized
for Altera's industry-leading FLEX 10KE and APEX families of programmable logic
devices (PLDs). The cores are ideal interfaces for networking and asynchronous
transfer mode (ATM) applications, ATM network interface cards (NICs), add drop
multiplexors, xDSL terminal adapters, and broadband access equipment. According
to a recent Dataquest report, the ATM access market will increase nearly 40
percent during the next year.
"These highly parameterizable UTOPIA cores are optimized to run at speeds of
over 80-MHz, and support local bus widths of 8 or 16 bits," said Craig Lytle,
senior director of Altera's Intellectual Property Business Unit. "When implemented
on Altera's PLDs, both UTOPIA cores expand on Altera's promise to deliver programmable
solutions that allow for early customization and fast time-to-market, with low
risk." The cores are downloadable from Altera's IP MegaStore™ web site
(IP MegaStore) for a free test drive
using the OpenCore feature.
About the UTOPIA Level 2 Cores
Altera's UTOPIA Level 2 Master MegaCore function is designed for use in ATM
layer devices that transfer data to and from PHY devices using the standard
UTOPIA bus. The UTOPIA Level 2 Master MegaCore function comprises a separate
transmitter and receiver; both support single PHY (SPHY), and multi PHY (MPHY)
operation modes. SPHY mode supports octet- or cell-level handshake; MPHY mode
supports cell-level handshake with up to 31 PHY devices.
The UTOPIA Level 2 Slave MegaCore function is designed for use in PHY layer
devices that transfer data to and from ATM devices using the standard UTOPIA
bus. The MegaCore function comprises a separate transmitter and receiver, and
includes internal 4-cell FIFOs.
Both cores support other features such as parity generation and detection and
local cell sizes of 52/53/54 Bytes.
Parameterized Using MegaWizard Plug-Ins
Altera's UTOPIA Level 2 cores can be parameterized with Altera's MegaWizard
Plug-In Technology. MegaWizard Plug-Ins allow users to parameterize megafunctions
to meet specific design objectives, greatly reducing the time spent in design.
In addition, MegaWizard parameters can be passed through to third-party design
tools, providing a highly integrated design solution.
The MegaWizard Plug-In capability is available in both Altera's fourth-generation
Quartus™ development environment and in the MAX+PLUS® II
development system. Both software platforms provide seamless integration with
tools from Cadence,
Mentor Graphics,
Synopsys,
Viewlogic, and other leading EDA vendors.
Pricing & Availability
The UTOPIA Level 2 Master (ordering code: PLSM-UTOPIA2MS) and UTOPIA Level
2 Slave (ordering code: PLSM-UTOPIA2SL) are currently available from Altera.
Each core is individually priced at $9,995 and comes with a complete user's
guide. In addition, simulation models are also provided for Modelsim and VCS,
enabling simulation in VHDL and Verilog environments. Customers can evaluate
their cores for free prior to licensing using the OpenCore feature, available
via Altera's IP Megastore web site.
Safe Harbor Notice
This press release contains "forward looking statements" which are made pursuant
to the safe harbor provisions of the Private Securities Litigation Reform Act
of 1995. Forward looking statements are generally preceded by words such as
"expects," "believes," "anticipates," "projects," or "intends." Investors are
cautioned that all forward-looking statements in this release involve risks
and uncertainty, including without limitation the risks that the Company's products
will not satisfy customer demands or that the product will not ship as scheduled.
Please refer to the Company's Securities and Exchange Commission filings, copies
of which are available from the Company without charge, for further information.
About Altera
Altera Corporation, The Programmable Solutions Company™, was founded
in 1983 and is a worldwide leader in high-performance, high-density programmable
logic devices and associated computer aided engineering (CAE) logic development
tools. Programmable logic devices are semiconductor chips that offer on-site
programmability to customers. The chips are programmed using tools that run
on personal computers or engineering work stations. User benefits include ease
of use, lower risk, and fast time-to-market. The company offers the broadest
line of CMOS programmable logic devices that address high-speed, high-density,
and low-power applications. Altera products serve a broad range of markets,
including telecommunications, data communications, computer peripherals, and
industrial applications. Altera common stock is traded on the Nasdaq Stock Market
under the symbol ALTR.
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