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For Release: February 28, 2000
Altera Expands DSP Leadership with Nine New Error Correction Cores For Communications Systems
- Altera Provides Low Cost and High Performance IP Cores for Forward Error Correction with Nine Cores Via Its Reed-Solomon Compiler, Viterbi Decoder, and Turbo Encoder/Decoder Solutions
- At 100 Mbits/sec, Viterbi Decoder is Fastest Available on the Market
- First Programmable Logic Company to Provide a Turbo Encoder/ Decoder IP Solution
San Jose, Calif., February 28, 2000--Adding to its robust Digital Signal Processing (DSP) product portfolio of more than 60 cores, Altera Corporation (Nasdaq: ALTR) today announced the availability of nine new high performance intellectual property (IP) cores. These cores are built around the new Reed-Solomon Compiler, Viterbi Decoder, and Turbo Encoder/Decoder solutions. When implemented in an Altera programmable logic device (PLD), these cores offer the lowest cost and highest performance for error correction systems in current and emerging wireless applications, such as digital video broadcast (DVB) and various transmission technologies. According to analyst Will Strauss of Forward Concepts, a Phoenix, Ariz.-based market research firm, wireless base stations are one of the key communication markets which benefit the most from these solutions when implemented in PLDs due to the re-configurability, design convenience, lower development cost and efficiency of PLDs.
"Altera already leads the market with error correction IP cores in PLDs. The introduction of these nine high performance, high-speed IP cores for programmable logic devices will further extend our capabilities," said Craig Lytle, vice president of Altera's Intellectual Property Business Unit. "Altera continues to push the technology envelope with the addition of the Turbo Encoder/Decoder cores, vital components for 3rd generation (3G) wireless base stations."
The new Reed-Solomon Compiler, Viterbi Decoder and Turbo Encoder/Decoder are all delivered with Altera's user-friendly MegaWizard™ graphical GUI application interface, through which designers can easily customize each error correction core to meet their specific performance parameters. Altera supplies these cores with the ability to do efficient functional simulation using industry standard VHDL and Verilog simulators. A bit-accurate compiled C model is also available for system-level simulation to calculate bit error rates.
Turbo Encoder/Decoder Megafunctions
Altera's Turbo Encoder/Decoder solution is ideal for error correction in next-generation wireless applications, such as the 3rd Generation Partnership Project (3GPP). It supports data rates in excess of 2 Mbits/sec, appropriate for the high-speed data services required by emerging 3G systems. The Turbo Encoder/Decoder has advanced technical features such as LogMAP algorithm for maximum error correction and includes a 3GPP compliant interleaver. Altera's Turbo Encoder/Decoder is targeted for use with the APEX™ 20K device family, fitting into an EP20K200E, priced at $43 in volume quantities.
Reed-Solomon Compiler Megafunctions
Altera's new Reed-Solomon Compiler supports six different types of Reed-Solomon cores including the Standard Encoder/Decoder, an Erasures add-on, Continuous Decoder, and Variable Encoder/Decoder. The Reed-Solomon Compiler also supports the CCSDS (Consultative Committee for Space Data Systems) standard, which is required for telemetry channel coding in wireless applications.
The compiler offers record encoding speeds of over 1 Gbit/sec and decoding speeds of 800 Mbits/sec. Altera's Reed-Solomon Compiler is fully parameterizable through the MegaWizard Plug-In feature, which allows the user to generate valid field and generator polynomials and create test vectors based on the parameters. Once parameterized, the core can be compiled with user-specified requirements, yielding an optimized netlist for a specific core. The standard Reed-Solomon Decoder fits into an EPF10K10A, which costs only $6.50 in volume quantities.
High Speed Viterbi Megafunction
For applications requiring Viterbi error-correction capabilities, Altera also offers a new high-speed Viterbi Decoder MegaCore™ function. With a 100 Mbits/sec decoding rate, it is the fastest Viterbi Decoder on the market. This parameterizable megafunction supports both soft and hard decision-making. The Viterbi Decoder features an integrated test-case generator for Additive White Gaussian Noise (AWGN). Designers can optimize the megafunction for either speed or error correction. The Viterbi Decoder fits into an EPF10K30A, priced at $8.25 in volume quantities.
Availability and Pricing
Altera's new Reed-Solomon Compiler and Viterbi decoder are all available now. The Turbo Encoder/Decoder will be available in March 2000. All products come complete with user guides. Customers can evaluate megafunctions for free prior to licensing via Altera's OpenCore™ feature, available at IP MegaStore.
The OpenCore feature allows the designer to download the function for a free test drive evaluation in the target design. The cores can be parameterized and fully verified with Altera's Quartus or MAX+PLUS® II development tool suites prior to licensing. The cores or a new subscription to Altera's design tools may be obtained by credit card at the Programmable eStore on the Altera web site, http://www.altera.com, or through Altera distributors worldwide.
The ordering codes and prices for the Reed-Solomon Compiler, Viterbi Decoder and Turbo Encoder/Decoder cores are shown in the following table:
| IP Core |
Ordering Code |
Price |
| Reed-Solomon Compiler |
| Standard Reed-Solomon Encoder |
PLSM-RSENC |
$1,995 |
| Standard Reed-Solomon Decoder |
PLSM-RSDEC |
$3,995 |
| Erasures (Add on Option) |
PLSM-HC-RSDEC/ERAS |
$4,995 |
| Continuous Reed-Solomon Decoder |
PLSM-HC-RSDEC/C |
$3,995 |
Variable Reed-Solomon Decoder
(Add on Option) |
PLSM-HC-RSDEC/V |
$2,995 |
| Variable Reed-Solomon Encoder |
PSLM-HC-RS-ENC/V |
$1,995 |
| Viterbi Decoder |
| High Speed Parallel Viterbi Decoder |
PLSM-HC-VITERBI/HS |
$9,995 |
| Turbo Encoder/Decoder |
| Turbo Encoder |
PLSM-TURBO/ENC |
$6,000 |
| Turbo Decoder |
PLSM-TURBO/DEC |
$34,000 |
Safe Harbor Notice
This press release contains "forward looking statements" which are made pursuant to the safe harbor provisions of the Private Securities Litigation Reform Act of 1995. Forward looking statements are generally preceded by words such as "expect," "believe," "anticipate," "project," "intends," or "will." Investors are cautioned that all forward-looking statements in this release involve risks and uncertainty, including without limitation the risks that the Company's products will not satisfy customer demands. Please refer to the Company's Securities and Exchange Commission filings, copies of which are available from the Company without charge, for further information.
About Altera Corporation
Altera Corporation, The Programmable Solutions CompanyTM, was founded in 1983 and is a leading supplier of programmable logic devices and associated logic development software tools. Programmable logic devices are semiconductor chips that can be programmed on-site, using software tools that run on personal computers or engineering workstations. User benefits include ease of use, lower risk, and fast time-to-market. Altera's CMOS-based programmable logic devices address high-speed, high-density and low-power applications in the telecommunications, data communications, computer peripheral, and industrial markets. Altera common stock is traded on the Nasdaq Stock Market under the symbol ALTR. More information on Altera can be obtained on the Internet at http://www.altera.com.
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