Copper Interconnect is Key Enabler for High-Bandwidth, High-Performance Optical Networking Applications
San Jose, Calif., November 20, 2000--Altera Corporation (Nasdaq: ALTR), a leading supplier of programmable logic devices (PLDs), today announced the APEX™ 20KC family, the first PLD family utilizing copper for all layers of metal interconnect. Working closely with wafer foundry and technology partner Taiwan Semiconductor Manufacturing Company (TSMC), Altera will build the APEX 20KC devices using 0.15-micron process technology with all-layer copper interconnect increasing core performance by 25 to 35 percent over comparable products based on a 0.18-micron aluminum process. Being the only PLD family manufactured using an all-layer copper interconnect technology, the APEX 20KC family is projected to be the fastest high-density product family in the industry. In addition to superior core performance, the APEX 20KC family features differential signaling for ultra high-speed I/O capabilities needed in high performance communications applications and system-on-a-programmable-chip (SOPC) designs.
The APEX 20KC family has been optimized with the fastest I/O performance in the marketplace by featuring the True-LVDS™ solution, which offers 840 Mbps per channel performance to support high-bandwidth, high-performance requirements often found in 10 gigabit Ethernet and optical WAN equipment. The APEX 20KC family supports complex communications applications such as dense wave division multiplexing (DWDM), SONET/SDH add-drop multiplexers, WAN routers and switches. The APEX 20KC family is based on Altera's popular APEX 20KE device family, the fastest growing product family in Altera's history.
"Altera is continually working with TSMC to drive process technology to the next level," said Steve Mensor, Altera director of product marketing, LUT products. "The collaboration between the two companies has allowed Altera to develop the APEX 20KC family using an all-layer copper interconnect, which is required to realize the significant performance improvements associated with copper."
Enhanced algorithms produced in the recent release of Quartus™ version 2000.09 improved core performance of the APEX architecture by over 30 percent. Additional performance improvements are expected in the next version of Quartus, which will be available in January. These Quartus improvements, when combined with the high-speed breakthrough of the APEX 20KC devices allow customers to obtain up to a 75 percent improvement in core performance in just six months.
"I/O bandwidth and core performance are the most important factors that customers are looking for today in programmable logic," added Mr. Mensor. "The combination of a dramatic improvement in the quality of results from Quartus and considerable silicon performance improvement from copper interconnect technology gives Altera a significant performance leadership position for high-end programmable logic applications."
Advanced Copper Process Technology
The all-layer copper process technology was developed in close cooperation with TSMC, the world's largest independent semiconductor foundry. All-layer copper interconnect replaces current aluminum/tungsten metalization systems while offering more flexibility in balancing metal pitch and thickness. Copper interconnect presents lower electrical resistance, thus improving performance by reducing interconnect delays seen in many integrated circuits. The low resistivity found in copper makes it one of the best known conductors of electricity, reducing interconnect delay by up to 40 percent.
Continuing to drive innovation, Altera and TSMC have collaborated on a 0.13-micron test chip utilizing all-layer copper interconnect. The test chip is used in the development of Altera's future PLD products based on 0.13-micron technology to be delivered late next year.
"TSMC and Altera have worked aggressively to prove the performance, power and density capabilities of TSMC's all-layer copper process," said Mike Pawlik, vice president of corporate marketing for TSMC. "Altera's new APEX 20KC family, which is based on a 0.15-micron, all layer copper technology, and the 0.13-micron test chip are clearly demonstrative of the success of these efforts."
APEX 20KC Features
Altera's APEX 20KC family will consist of six devices covering a density range from 100,000 to 1.5 million gates (2.4 million maximum system gates). The APEX 20KC family supports 840 megabits per second (Mbps) low voltage differential signaling (LVDS) with its True-LVDS technology. All devices in the APEX 20KC family feature Altera's unique MultiCore™ architecture, which combines LUT-based logic with flexible embedded memory. Altera's APEX 20KC family also contains clock-management circuitry with up to four PLLs. Each embedded system block (ESB) within a MegaLAB™ structure contains 2,048 programmable bits that can be configured to support dual-port RAM, ROM, and CAM. CAM accelerates applications such as network switching, packet routing and pattern recognition that require fast searches of databases, lists and patterns.
Software Support
Altera's APEX 20KC devices will be supported by Quartus, Altera's fourth-generation development environment. Altera's Quartus software was developed to support system-level designs and features good-as-native links to industry-leading, third party tools from Mentor Graphics, Synopsys, Synplicity, and other leading EDA vendors. It also features the SignalTap™ embedded logic analysis tool for in-system hardware debugging. Altera's Quartus software meets the challenges of designing for multi-million gate devices and enables SOPC design methodologies. It supports major operating systems, including Windows NT, Windows 98, Windows 2000, Sun Solaris, and HP-UX.
Availability, Packaging, and Pricing
The APEX 20KC family will be available in a wide range of packages, including Altera's FineLine BGA™ packages, and will begin shipping in Q1 2001. The first device available will be the EP20K600C with a volume price of $150 by end 2001. Quartus software support for these new devices will be available in January 2001.
Safe Harbor
This press release contains "forward-looking statements" that are made pursuant to the safe harbor provisions of the Private Securities Litigation Reform Act of 1995. Forward-looking statements are generally preceded by words that imply a future state such as "expected" or that imply that a particular future event or events will occur such as "will". Investors are cautioned that all forward-looking statements in this release involve risks and uncertainty, including without limitation the risk that future performance is dependent on product development schedules, the design performance of software and other tools, as well as the company's and third parties' development technology and manufacture capabilities. Please refer to the company's Securities and Exchange Commission filings, copies of which are available from the company without charge.
About Altera
Altera Corporation, The Programmable Solutions Company®, was founded in 1983 and is a leading supplier of programmable logic devices (PLDs). Altera's CMOS-based PLDs are user-programmable semiconductor chips that enhance flexibility and reduce time-to-market for companies in the communications, computer peripheral, and industrial markets. By using high performance devices, software development tools, and sophisticated intellectual property cores, system-on-a-programmable-chip (SOPC) solutions can be created with embedded processors, memory, and other complex logic together on a single PLD. Altera common stock is traded on The Nasdaq Stock Market under the symbol ALTR. More information on Altera is available on the Internet at http://www.altera.com.
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