Altera Provides Comprehensive Offering of Compliant Products within its MAX® and Configuration Device Families
San Jose, Calif., September 25, 2000--Altera Corporation (Nasdaq: ALTR), a leading programmable logic device (PLD) supplier, today announced compliant devices and development support for the IEEE 1532 specification for in-system programming (ISP). The objective of the ISP standardization effort is to significantly simplify manufacturing support for ISP devices. The standardization effort builds on the 1149.1 JTAG boundary-scan architecture standard by addressing both silicon and software issues to create a simplified and homogeneous ISP environment. The IEEE 1532 specification supports a variety of device types, including memory devices and PLDs. Altera has supported JTAG-based ISP in its MAX® 7000 family since 1996, driving the MAX 7000 architecture to be the most popular ISP CPLD architecture in the industry.
"The evolution of in-system programming has provided flexibility and efficiency to consumers of programmable logic," said Tim Colleran, Altera director of MAX product marketing. "The recent standardization efforts will eventually bring a whole new set of manufacturing efficiencies via common programming tools and concurrent programming."
In addition to its participation in the definition and standardization of the IEEE 1532 specification, Altera offers a wide range of ISP-based PLDs that support the new specification. These products include Altera's MAX 7000B, MAX 7000A, MAX 7000, MAX 3000A,
MAX 9000, and Configuration Device families.
"Once the IEEE 1532 standard is fully implemented, I expect the specification to simplify our production test flow. It is important for EMC to see the support and participation of key suppliers, such as Altera, in the standardization effort," said Robert J. Russell, test engineering manager at EMC Corporation. "The next step in the standardization process is to complete the software portion of the specifications."
The new IEEE 1532 standard is complementary to the JEDEC-approved Jam™ Standard Test and Programming Language (STAPL). The IEEE 1532 standard is a hardware standard that defines the actual ISP algorithm, while Jam STAPL is a software standard that defines the file format that stores the programming information for the chain of devices. Jam STAPL rounds out a complete ISP solution by addressing specific issues with ISP via an embedded processor.
"The success of any specification requires the participation of industry leaders to define and drive the specification. I applaud Altera's support for the standardization effort to date and the commitment to completing the software portion of the specification," said Ken Parker, engineer/scientist at Agilent Technologies and technical editor for the 1532 specification.
About Altera
Altera Corporation, The Programmable Solutions Company®, was founded in 1983 and is a leading supplier of programmable logic devices (PLDs). Altera's CMOS-based PLDs are user-programmable semiconductor chips that enhance flexibility and reduce time-to-market for companies in the communications, computer peripheral, and industrial markets. By using high performance devices, software development tools, and sophisticated intellectual property cores, system-on-a-programmable-chip (SOPC) solutions can be created with embedded processors, memory, and other complex logic together on a single PLD. Altera common stock is traded on The Nasdaq Stock Market under the symbol ALTR. More information on Altera is available on the Internet at http://www.altera.com.
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