Altera Introduces Stratix™ Device Family-Industry's Fastest PLDs
40 Percent Performance Boost with Industry's Most Memory, Logic Elements and DSP Functionality
San Jose, Calif., February 11, 2002 -- Altera Corporation (Nasdaq: ALTR) today introduced the Stratix™ device family, the industry's largest and fastest programmable logic devices (PLD). With a die size that is 35 percent smaller than previous architectures, the Stratix device family offers up to 10 Mbits of RAM and up to 114,140 logic elements, delivering more than three times the memory and 21,000 more logic elements than its closest competitor. Built on a new routing architecture, the Stratix devices yield an unprecedented 40 percent increase in performance from Altera's APEX™ II devices, making the new device family the industry's fastest PLDs. Additionally, with the inclusion of dedicated DSP functionality, the Stratix devices address DSP and computationally complex applications up to twice as fast as any other PLD in the industry.
"The introduction of our Stratix devices ushers in a new era for programmable logic," said John Daane, president and CEO of Altera. "Building on our history of innovation, Altera is once again breaking PLD boundaries and delivering what are today the fastest devices in the industry. The Stratix devices achieve the highest levels of integration with the most memory, logic elements and DSP functionality ever in a PLD, thus giving our customers an ASIC-strength product with all the benefits of programmable logic."
The recently announced Quartus® II version 2.0 design software, which is now shipping to all Altera customers, fully supports the Stratix device family. Early access to the design software was delivered last November to Altera's major customers. To read what customers are saying about Stratix visit http://www.altera.com/corporate/cust_successes/customer_quotes/cqt-index.html#stratix.
"With the tight synchronization between the devices and our design software, we're offering a very powerful and easy-to-use solution to designers or teams of designers who now face higher levels of system integration," continued Daane.
Silicon efficiency was achieved in all areas including the MultiTrack™ routing, logic elements, embedded memory and I/O structures. All told, compared to previous generations, the Stratix architecture achieves die size reductions of more than 35 percent while featuring eight times more RAM bits as well as dedicated DSP functionality, on-chip termination resistors and advanced system clock management features.
- TriMatrix™ Memory - With a new TriMatrix™ memory structure, Stratix devices offer the most memory bits, the highest memory-to-logic ratio and the highest memory bandwidth of any PLD family. Consisting of three memory sizes- 512-bit M512 blocks, 4-kbit M4K blocks and 512-kbit MegaRAM™ blocks- TriMatrix memory addresses different classes of memory-intensive applications.
- DSP Blocks - To achieve higher levels of DSP performance, Altera embeds dedicated DSP blocks that offer predictable and reliable performance of 250MHz for DSP applications such as rake receivers, voice over IP (VoIP), orthogonal frequency division multiplexing (OFDM), image processing applications and multimedia entertainment systems. The DSP blocks eliminate performance bottlenecks in DSP applications commonly found in multiplier-only implementations.
- Differential I/O - Altera is the only company that offers True-LVDS™ circuitry, which includes embedded SERDES, multi-mode clocking, data realignment and on-chip termination resistors for all of its differential channels. The Stratix device family offers up to 116 high-speed differential I/O channels, with up to 80 channels optimized for 840 Mbps operation. The differential I/O capabilities in The Stratix devices are ideal for interface bridging, backplanes, chip-to-chip communications and other subsystems. The Stratix devices are designed to support up to 4 high bandwidth interfaces such as 10 Gigabit Ethernet XSBI, POS-PHY L4, Hypertransport, Rapid IO, SFI-4 and UTOPIA IV in one device.
- Terminator™ Technology - Stratix devices are the first PLDs to offer on-chip termination for differential I/Os. The devices also support serial and parallel termination for single-ended I/O. On-chip termination is essential for reducing reflections and improving signal integrity in high-speed systems to maximize system performance. In addition, Terminator™ technology simplifies board design and reduces board space by minimizing the number of external resistors required on a PCB.
- Dedicated External Memory Interfaces - In addition to offering abundant on-chip memory resources with the TriMatrix memory structure, Stratix devices also feature dedicated interfaces for standard memory technologies such as DDR SDRAM, QDRII SRAM and ZBT SRAM devices with support for data transfer rates of up to 668 Mbps. Designers can easily connect these external memory devices to Stratix devices without degrading data access performance or increasing development time.
- Extensive PLLs and Clock Management Circuitry - Stratix devices offer the highest number of PLL taps and global clocks in the PLD industry. With up to 12 PLLs and up to 40 unique system clocks per device, Stratix devices are built to function as a central clock manager. These devices are the first PLDs to offer on-chip PLL features for system-level clocking management previously found only in high-end discrete PLL devices. These features include clock switchover, PLL re-configuration, spread spectrum clocking, and programmable bandwidth. This comprehensive timing solution eliminates the need for multiple discrete timing devices on a board, thereby resulting in real estate and overall systems cost savings.
HardCopy™ Program Support for Stratix Devices
The Stratix device family will also be supported by Altera's HardCopy™ program, giving customers the option of migrating their high-density system-on-a-programmable-chip (SOPC) designs to a low cost, hard-masked solution for volume production.
Nios™ Soft-Core Support for Stratix Devices
Designers can immediately take advantage of the Nios embedded soft-core processor with Stratix, leveraging Altera's flexible CPU technology to create custom, high-performance systems on a programmable chip.
Availability, Packaging, Pricing
The Stratix device family consists of eight members, ranging in density from 10,570 logic elements and approximately 1 Megabit of on-chip memory to 114,140 logic elements with up to 10 Megabits of on-chip memory. All devices are based on ball grid array (BGA) technology and will be offered with both 1.27-mm and 1-mm ball spacings. The first device, the EP1S25, will be sampling in the second quarter with volume pricing starting at $125 in 2003.
Stratix device family support in the Quartus II version 2.0 design software is available now. Further information and support is available from more than 20 application notes and other documents written specifically for the Stratix device family, as well as an industry-leading technical support team that offers in-depth Stratix device design expertise. Altera customers also have access to a new online resource that provides solutions for all their memory, DSP, and I/O design requirements. Now available at http://www.altera.com/solutioncenters, these new Solution Centers allow customers access to all related information in a central location.
For more information about the Stratix device family including a product backgrounder, answers to frequently asked questions and related White Papers about Stratix visit: http://www.altera.com/corporate/news_room/presskit/nr-stratix.html.
About Altera
Altera Corporation (Nasdaq: ALTR) is the world's pioneer in system-on-a-programmable-chip (SOPC) solutions. Combining programmable logic technology with software tools, intellectual property, and technical services, Altera provides high-value programmable solutions to approximately 14,000 customers worldwide. More information is available at http://www.altera.com.
Editor Contacts:
| Anna del Rosario Altera Corporation (408) 544-6397 newsroom@altera.com |
