Altera's Stratix^™ Devices Deliver A Revolutionary Approach to DSP Design

DSP Blocks in Stratix^™ Devices Provide Design Flexibility and Highest Data Throughput

San Jose, Calif., February 21, 2002 -- The DSP blocks in Altera Corporation's (Nasdaq: ALTR) newly announced Stratix^™ devices offer predictable and reliable performance of 250 MHz to provide data throughput performance of up to 2.0 GMACS per DSP block, the company announced today. The 28 dedicated DSP blocks embedded in the largest Stratix device, the EP1S120 device, can provide a combined throughput that is over five times higher than the leading digital signal processors today.

"The Stratix device family is an avant-garde, forward thinking innovation that presents a very compelling reason for DSP designers to turn to programmable logic for many of their applications," said Will Strauss, DSP industry analyst and president of Forward Concepts. "The Stratix device family s dedicated DSP block circuitry dramatically changes the landscape for implementing high-performance DSP applications in programmable logic."

"Altera's revolutionary approach to DSP design is a major breakthrough for programmable logic," said Steve Mensor, Altera's senior director of product marketing for new products. "The DSP blocks in the Stratix devices are ideal for implementing complex DSP functions that require high data throughput. This innovation in DSP design reduces the cost of implementation and dramatically increases performance."

The Stratix DSP blocks, which consist of hardware multipliers, adders/subtractors, accumulators, and pipeline registers, are high-performance embedded arithmetic units that are optimized for applications such as rake receivers, voice over Internet protocol (VoIP) gateways, orthogonal frequency division multiplexing (OFDM) transceivers, image processing applications, and multimedia entertainment systems.

Flexible, efficient, and valuable for a variety of applications that require high data throughput, these DSP blocks can implement a variety of typical DSP functions, like finite impulse response (FIR) filters, fast Fourier Transform (FFT) functions, correlators, and encryption/decryption functions, as well as barrel shifters, crossbar switches, and shifters. Altera's approach to DSP design makes Stratix devices an ideal choice for the wireless communication, telecommunication, video, and image processing markets.

Time-Domain Multiplexing Improves Throughput and Device Utilization

By using the on-chip PLLs for time-division multiplexing (TDM) of the high-performance DSP blocks, the amount of logic resources used can be dramatically reduced. TDM is the process of time-slicing the same hardware resources. With TDM, a designer can use a single high-speed DSP block to perform computations for many channels of lower speed, similar DSP functions.

For example, an application that requires a 100-Tap FIR filter operating at 10 MHz implemented in Logic Elements (LEs) with maximum performance of 100MHz would take 12,000 LEs. The same design can be implemented in a single DSP block that operates at 250 MHz, resulting in a die area savings of 98 percent.

Stratix DSP Block Design Support

Design support for the DSP blocks in Stratix devices is provided by Altera's Quartus^® II version 2.0 design development software, which is a complete design entry, compilation, and verification environment for Altera programmable logic devices (PLDs). The Quartus II version 2.0 design software automatically recognizes arithmetic functions in hardware description language (HDL)-based and library of parameterized module (LPM)-based design formats, and targets them for implementation in DSP blocks. DSP developers can also use Altera's DSP Builder, which seamlessly links The MathWorks MATLAB and Simulink environments familiar to DSP engineers with Quartus II design software. Designers can also visit the new DSP Solutions Center at http://www.altera.com/dsp to access all the latest information on Altera's latest DSP solutions from a central on-line location.

For more information on the DSP capability of Stratix devices, go to: http://www.altera.com/products/devices/stratix/features/stx-dsp.html.

About Stratix Devices

Stratix devices are based on a 1.5-V, 0.13-µm, all-layer copper SRAM process, with densities ranging from 10,570 to 114,140 logic elements (LEs) and up to 10 Mbits of RAM. Stratix devices offer up to 28 DSP blocks with up to 224 embedded multipliers, optimized for DSP applications that require high data processing. Stratix devices support various differential I/O electrical standards such as LVDS, LVPECL, PCML, and HyperTransport, as well as high-speed interfaces, including UTOPIA IV, SPI-4 Phase 2, SFI-4, 10G Ethernet XSBI, RapidIO, HyperTransport, and others. Stratix devices also offer a complete clock management solution with its hierarchical clock structure and up to 12 phase-locked loops (PLLs). More information about the Stratix device family is available at http://www.altera.com/stratix.

For more information about the Stratix device family including a product backgrounder, answers to frequently asked questions and to read what customers are saying about Stratix visit: http://www.altera.com/corporate/news_room/nr-index.jsp.

About Altera

Altera Corporation (Nasdaq: ALTR) is the world's pioneer in system-on-a-programmable-chip (SOPC) solutions. Combining programmable logic technology with software tools, intellectual property, and technical services, Altera provides high-value programmable solutions to approximately 14,000 customers worldwide. More information is available at http://www.altera.com.

Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations and all other words that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders.

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