For Release: November 05, 2004
***MEDIA ALERT***
Benefits of Altera's Dense, High-Performance Designs Displayed at Denali MemCon
| What: |
Robert Blake, Altera’s vice president of product planning, will be in the panel discussion “ASIC, Structured ASIC, and FPGA: Defining the SoC Methodology,” examining each of these alternatives to the problems of fast time-to-market, low-cost, and shortened design time for rapid response to fast moving markets. In addition, Altera will be presenting a paper explaining how engineers can resolve FPGA design challenges with Altera’s complete DDR2 interface solutions to lower risks, maximize performance, and accelerate time-to-market. Also, stop by the Altera booth to see demonstrations of our memory interface portfolio on Stratix® II high-speed I/O and memory boards.
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When: |
Tuesday, November 9
Panelist: Robert Blake, vice president of product planning
1:15 p.m.– 2:15 p.m. PST
Panel: ASIC, Structured ASIC, and FPGA: Defining the SoC Methodology
Tuesday, November 9
Presenter: Sanjay Charagulla, system architect
3:45 p.m.– 4:15 p.m. PST
Title: Designing DDR2 Memory With Altera Stratix II FPGAs
Wednesday, November 10
Presenter: Vipul Badoni, senior manager, high-speed applications
2:15 p.m.– 2:45 p.m. PST
Title: Ensuring Success in High-Speed System Design
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Where:
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Denali MemCon San Jose
Altera Booth #233
The Westin Santa Clara Hotel
5101 Great America Parkway
Santa Clara, California 95054
Phone: 408-986-0700
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For Additional Information:
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www.memcon.com
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