For Release: August 30, 2005
***MEDIA ALERT***
Altera Hosts High-Speed Serial Interconnect Seminar With Industry Experts
San Jose, Calif., August 30, 2005—
What:
Altera Corporation (NASDAQ: ALTR) is hosting its second High-Speed Serial Interconnect Seminar aimed at helping designers understand the complexities of high-speed serial link interconnects. Leading industry experts will discuss how to select and design with connectors, transceivers and boards for multi-gigabit serial data. Kevin M. Roselle, CTO of Bayside Design, will deliver the keynote presentation, “Right First-Time Design for Multi-Gigabit Serial Links.” As an expert in all aspects of high-speed design, Mr. Roselle will discuss some of the challenges encountered when designing channels for multi-gigabit operation. Presentations will also be delivered by industry experts from Sanmina, Teradyne, Tyco and Altera. The Altera presentation will highlight key features of their upcoming Stratix® II GX FPGA family with embedded transceivers.
Agenda:
September 22, 2005
| 8:30 a.m. |
Breakfast/Registration
|
| 9:00 a.m. |
Right First-Time Design for Multi-Gigabit Serial Links
Kevin M. Roselle
CTO
Bayside Design
|
| 10:00 a.m. |
Silicon-Driven Signal Integrity Tools
Jim Tavacoli
Senior Director of Component Product Planning
Altera Corporation
|
| 11:00 a.m. |
Design for System Scalability From 622 Mbps to 6.25 Gbps
Gautam Patel
Signal Integrity Engineer
Teradyne
|
| 11:45 a.m. |
Looking Ahead to 10 Gbps to Understand How to Design at 6.25 Gbps & Lower
John D'Ambrosia
Manager of Semiconductor Relations
Tyco Electronics, Tyco
|
| 12:30 p.m. |
High-Speed PCB Design Techniques for AdvancedTCA
Barry Kirkorian
Product Manager
Sanmina-SCI Corporation
|
For more information or to register for the event, please visit: www.altera.com/highspeedserial
Where:
Crowne Plaza, Worcester
10 Lincoln Square
Worcester, MA 01608
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