For Release: December 12, 2007
Stratix III FPGAs Achieve 533-MHz DDR3 Interface Performance
Altera Devices Enable Highest Memory Bandwidth Available in a Programmable Logic Device
San Jose, Calif., December 12, 2007—Altera Corporation (NASDAQ: ALTR) today announced it has achieved DDR3 memory interface speeds in excess of 1067 Mbps with its Stratix® III FPGAs, providing a 33 percent advantage in memory performance over competing FPGA solutions. This higher memory bandwidth enables new communications, computing and video processing applications that were either previously impossible or required doubling the number of memory banks. Altera’s Stratix III FPGA family is the industry’s only FPGA to demonstrate full compliance to the JESD79-3 JEDEC DDR3 SDRAM standard, including the performance-critical read/write-leveling specification for maximum system performance.
“The performance, cost, density, and power benefits that DDR3 memory provides, in conjunction with the highest performance and lowest power of Stratix III FPGAs, is essential to a wide range of communications, signal processing, high-performance computing and image processing applications,” said David Greenfield, senior director of product marketing, high-end products at Altera. “Stratix III FPGAs are the only FPGAs designed for fully compliant DDR3 SDRAM DIMM support and the only FPGAs to exceed 533 MHz operation.”
In addition to higher memory interface speeds, Stratix III FPGAs demonstrate 29 percent lower power consumption and a 25 percent performance advantage, as compared to competing solutions, making the device family ideal for high-performance applications that require the lowest possible power.
Designed to address the benefits of DDR3 memory, Altera’s Stratix III family is the only FPGA in the industry to include read and write leveling, I/O delay for DQ de-skew, dynamic on-chip termination, and the use of a reconfigurable phase-locked loop (PLL) to compensate for voltage and temperature variations. In addition, Altera’s Quartus® II software version 7.2 includes a DDR3 PHY wizard and controller intellectual property (IP), which substantially simplifies high-performance memory interface design by automatically adapting to DIMMs from a variety of memory suppliers.
Availability
Altera® Stratix III FPGAs featuring DDR3 memory bandwidth capabilities of 533 MHz are available now. To learn more about Altera’s Stratix III FPGAs, visit www.altera.com/stratix3. To learn more about how easily FPGAs can interface with DDR3 SDRAM, visit Altera’s webcast at www.altera.com/education/webcasts/all/wc-2007-ddr3.html.
About Altera
Altera programmable solutions enable system and semiconductor companies to rapidly and cost-effectively innovate, differentiate and win in their markets. Find out more at www.altera.com.
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