Altera Increases Productivity for High-Performance DSP Designs by an Order of Magnitude

DSP Builder Version 8.0 Features Second-Generation Timing-Driven Simulink Synthesis Technology

San Jose, Calif., June 30, 2008—Targeting high-performance digital signal processing (DSP) designs, Altera Corporation (NASDAQ: ALTR) today announced its DSP Builder tool version 8.0, featuring second-generation model-based synthesis technology. This technology allows DSP designers for the first time to automatically generate timing-optimized RTL code based on high-level Simulink design descriptions. With this new DSP Builder feature, designers can achieve high-performance design implementations, running at near-peak FPGA performance, in a matter of minutes. This is a significant productivity savings compared to the hours, if not days, required to hand-optimize HDL code.

“DSP Builder’s second-generation model-based synthesis technology allows customers to use Simulink as the modeling, simulation and implementation environment of choice for high-performance DSP designs,” said Ken Karnofsky, marketing director for signal processing and communications at The MathWorks. “This technology allows designers to vastly improve their productivity as they implement DSP functionality on Altera’s FPGAs.”

Designing multi-channel signal processing datapaths in applications such as multi-carrier, multi-antenna RF processing in wireless basestations, the new DSP Builder second-generation synthesis technology delivers dramatic productivity gains. The DSP Builder tool automatically adds pipelined stages and registers, and implements time division multiplexing to generate highly optimized designs for functions such as digital upconversion (DUC), downcoversion (DDC), crest factor reduction (CFR) and digital predistortion (DPD). This greatly enhances productivity and enables users to perform system level design exploration rapidly, and to easily scale their design for varying carrier bandwidths, number of carriers, antennas, and sectors. DSP Builder version 8.0 includes design examples for multi-antenna, multi-carrier WiMAX and WCDMA DUC and DDC designs.

“Altera continues to set the standard for FPGA design productivity, including high-performance DSP designs,” said Chris Balough, marketing director for software, embedded, and DSP at Altera. “The innovative synthesis technology included in DSP Builder version 8.0 delivers a timing-driven FPGA implementation environment that allows designers to get the system performance they require with the push of a button—enabling an order-of-magnitude productivity gain.”

Availability

Used with Altera’s Quartus^® II design software, DSP Builder version 8.0 is available now for purchase. More information about Altera^® DSP solutions and its DSP Builder tool is available at www.altera.com/dsp. Simulink is available today from The MathWorks at www.mathworks.com.

About DSP Builder

DSP Builder is the leading synthesis technology for implementing Simulink designs in a high-performance FPGA platform quickly and effortlessly. Altera’s DSP Builder reads Simulink model files (.mdl) that are built using DSP Builder/MegaCore^® blocks and generates VHDL files and tool command language (Tcl) scripts for synthesis, hardware implementation and simulation. This technology shortens DSP design cycles by creating the hardware representation of a DSP design in an algorithm-friendly development environment.

About Altera

Altera programmable solutions enable system and semiconductor companies to rapidly and cost-effectively innovate, differentiate and win in their markets. Find out more at www.altera.com.

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