Systems architected for HardCopy® ASICs enable true hardware and software co-design and tremendously reduce system time-to-market and time-to-profit. The simplicity of using Altera's Quartus® II software tool, combined with intellectual property (IP) from Altera and our partners, allows you to design both the FPGA and ASIC simultaneously. Simply select the appropriate Stratix® series FPGA and HardCopy companion device in the Quartus II software and start your design—it's that easy.
Additionally, because Altera performs all design-for-test work in the HardCopy Design Center, no effort is required on your part for test insertion and/or test vector generation. Figure 1 shows the HardCopy design flow.
Figure 1. HardCopy Design Flow
Take advantage of the quick system development tools and other capabilities available in Quartus II software such as SOPC Builder and the TimeQuest timing analyzer.
- SOPC Builder enables you to quickly build and integrate a system on a chip (SOC) using your IP and/or third-party IP blocks.
- TimeQuest timing analyzer, Altera’s easy-to-use, second generation ASIC-strength timing analyzer, offers native support for Synopsys Design Constraints (SDC) format and full scripting capabilities, as well as a complete GUI environment for creating constraints and timing reports.
Altera’s PowerPlay power analysis and optimization technology and early power estimator enable power design capabilities for every stage of your design with:
- Early power estimation for determining power budget for your design and board up-front allow you to design from the start with power in mind
- Accurate power estimation with detailed analysis during the design cycle
- Automatic push-button power optimization of static and dynamic power consumption
- Built-in power optimization advisor
Additionally, Altera and our partners offer a wide variety of intellectual property (IP) that allows your design teams to focus on your differentiating technology without re-inventing already available IP.