The HardCopy® II ASIC, Altera's third-generation family in the HardCopy series, continues to deliver low risk, low total cost, and fast time-to-market/fast time-to-profit solutions for your custom logic needs.
If your applications require any combination of reduced power, lower bill of materials (BOM) cost, increased performance, single event upset (SEU) immunity, and security, look to HardCopy ASICs. Its system development methodology allows you to do one design, using one methodology, one tool, and one company, and then ramp production when it makes sense for your application. No other company can offer you a lower risk alternative or faster development.
- W = wire bond
- ASIC gates calculated as 12 gates per LE, 5000 gates per 18 x 18 multiplier (RAMs, PLLs, test circuitry, I/O registers not included in gate count)
- PLL = phase-locked loop
|Table 2. HardCopy II ASIC Industrial Temperature Support|
To get started with your designs, see HardCopy II Getting Started.