The HardCopy® system development methodology enables you to seamlessly prototype HardCopy II ASICs using high-performance Stratix® II FPGAs at full system speed. HardCopy II ASICs can provide up to twice the core logic performance over the FPGA prototype.
The performance improvement is due to the following:
- Shorter routing due to much smaller die compared to FPGA
- Fewer logic levels for certain combinatorial logic paths
- Flexibility in HCell macro placement
The performance advantage of HardCopy II ASICs is further enhanced with the ASIC-strength of the Quartus® II design software. You use SDC-formatted timing constraints to precisely define and analyze your timing requirements—one SDC for the ASIC and one SDC for the prototyping FPGA. You can also use physical synthesis and incremental compile features to further improve design performance. To take maximum advantage of this approach, Altera recommends that you use the HardCopy Device First approach in the Quartus II design flow.
Prototyping your system at reduced speed of the final silicon still offers you tremendous verification benefits over simulation or traditional emulation approaches.
For example, when the clock for the HardCopy II ASIC device is targeted at 300 MHz, and the Stratix® II FPGA prototype is running at 150 MHz, there are approximately 13 teracycles of emulation every 24-hour period – far surpassing other simulation or emulation approaches.