HardCopy® II ASICs are architected to deliver excellent single event upset (SEU) immunity for your high-reliability designs.
HardCopy II ASICs are built using an array of fine-grained HCell blocks. HCells are configured and grouped together by via-programming to construct Stratix® II FPGA adaptive logic module (ALM) combinational and sequential logic functions and digital signal processing (DSP) blocks.
The connections between HCells are hard-wired after via-programming. The high SEU tolerance nature of HardCopy II ASICs is due not only to the hard-wiring, but also to the improved architecture of sequential elements. Contact your Altera® representative for details.
ASICs Aligned for High-Performance Designs
HardCopy II ASICs are well aligned for designs in high-performance computing, storage, military, and aerospace applications.
For the military and aerospace markets, the ability to provide high immunity to SEU, low device power, and single-chip-live-at-power-up make HardCopy II devices ideal for use in avionics, missiles, modems, sensors, radios, and unmanned vehicle applications.
HardCopy II ASICs support military temperature range (-55°C to +125°C). Also, the HardCopy II ASIC design and manufacturing flow are compliant with the International Traffic in Arms Regulations (ITAR) established by the U.S. Department of State. This compliance allows designers of U.S. military electronics systems to take advantage of a secure HardCopy II design flow using the HardCopy system development methodology.