HardCopy® III ASICs deliver the lowest risk, lowest total cost, fastest time-to-market, and fastest time-to-profit solution for your custom logic needs.
The HardCopy methodology allows you to seamlessly prototype your system with Stratix® III FPGAs and completely prepare your system for production, prior to ASIC design handoff. Altera’s HardCopy Design Center uses a proven turnkey process to implement the low-cost, low-power, functionally-equivalent, pin-compatible HardCopy III device. This methodology is more than just a fast ASIC development methodology, it is the ultimate system development methodology.
Built to enable seamless prototyping
HardCopy III ASICs are built from the ground-up to enable Stratix III FPGA-based seamless prototyping. First, base members of the HardCopy III family are defined by using Stratix III compatible I/O module rings. Then, the base dies are embedded with equivalent hard intellectual property (IP) blocks, such as I/O buffers, clock networks, phase-locked loops (PLLs), and memory blocks, from Stratix III FPGAs. The remaining die area is filled with proven, fine-grained HCells for logic. The result is an ASIC that is a seamless drop-in replacement to the prototyping FPGA on your system board.
Altera’s Quartus® II development software suite offers the industry’s only “design-once” tool for both HardCopy ASICs and prototyping FPGAs. You simply use one register transfer level (RTL), one IP set, and one design tool for two device implementations.
More system integration
HardCopy III ASICs are built to enable more system integration with increased capabilities.
- High density
- 2.7M to 7M usable ASIC gates (not including I/Os, PLLs, and built-in test logic)
- 4.2 Mbit to 16.3 Mbit on-chip memory
- 4 to 12 PLLs
- Low power consumption comparable to standard-cell ASICs
- Typical 50 percent power reduction from the Stratix III FPGA prototype
- Stratix III device family leads the FPGA industry in low power consumption
- Application-optimized packaging
- Low cost wire bond
- Cost-optimized flip chip
- Performance-optimized flip chip
The strength of the HardCopy methodology is Altera's premier Quartus II development software suite and FPGA-based front-end prototyping design process. You can start your HardCopy III ASIC design today by targeting your design to an appropriate Stratix III FPGA in the latest Quartus II design software.
For further details, contact your local Altera sales office, representative, or distributor.