Altera’s complete system development methodology, enabled by HardCopy® III ASICs, delivers the lowest risk, lowest total cost, fastest time-to-market, and fastest time-to-profit solution that is ideal for many different end markets and applications:
- Computer, Storage, and Printer
- Test and Measurement
- Commercial Avionics and Military
The wireless end market is evolving at a rapid pace toward next-generation mobile broadband access systems such as WiMAX and 3GPP long-term evolution (LTE).
HardCopy III ASICs are well suited for wireless basestation applications such as transceiver, baseband, power amplification, control processing, communication interface, and so on. You not only benefit from the cost-effective, power-efficient, digital signal processing (DSP)-rich nature of the HardCopy III ASICs used in your production system, but also benefit in the development phase by using the Stratix® III E FPGA-based prototypes and having your wireless system in production quality before committing to the ASIC design handoff.
The Stratix III E FPGA’s programmability is valuable when developing the complex DSP functions needed to send and receive complex RF modulation to perform baseband generation and to get the maximum efficiency from amplifiers and antennas. At such high rates, simulation is not effective in examining the effects of real-world noise and uncertainty. You can refine and test systems designed with FPGAs much more effectively than those designed with fixed approaches. A DSP processor is flexible because code can be changed. But even the fastest DSP processor is not as efficient as the Stratix and HardCopy devices because their abundant multipliers and registers allow you to implement DSP functions in parallel.
Although HardCopy III ASICs are not themselves re-programmable, when combined with Stratix III FPGAs they offer the ability to wait to the last moment before making the transition from FPGA to ASIC for manufacturing. Further, it is possible to start initial production with Stratix III FPGAs and only go to HardCopy III ASICs once a system is customer-proven in field trials. This flexibility and time-to-market advantage is not possible with standard cell ASICs.
Computer, Storage, and Printer
Computer, storage, and printer markets are fast-moving markets. New products are introduced, sold, and replaced at a very fast pace. Being able to develop new products quickly using the HardCopy enabled system development methodology provides manufacturers with a significant competitive advantage. Further, with very short product life cycles in these markets, the HardCopy methodology enables companies to develop products very cost effectively.
Product differentiation is very important. However, with the development cost of cell-based ASICs sky-rocketing, manufacturers often feel that ASSPs are their only option. Using only ASSPs makes a product undifferentiated from competitors, limiting competition to cost only. HardCopy III ASICs enable differentiating ASIC functionality in the moderate-volume, higher-end segments of the computing, storage, and printer markets.
HardCopy III ASICs are also ideal for ultra-high reliability applications such as mainframe computers because of their high single event upset (SEU) tolerance and low power requirements.
With the push toward high-resolution images and real-time diagnosis, the data transmission and image processing requirements in medical diagnostic equipment are becoming more and more sophisticated.
HardCopy III ASICs that are prototyped with Stratix III E FPGAs provide the high-performance DSP needed to collect, process, and display the data, the ability to transmit and receive data using high-speed LVDS differential interfaces, and the ability to buffer data using high-speed external memory interfaces.
The medical equipment industry requires clinical trials to test the operation of products. Because HardCopy III ASICs and Stratix III FPGAs are designed to be drop-in replacements to each other, you use the FPGA in the trials so that any changes in signal processing can be made quickly, and the design can complete the trials as quickly as possible. Once the medical product is approved and ready for production, you can implement the design in a pin- and package-compatible HardCopy III ASIC.
Today, a typical automotive design cycle is approximately 24 to 36 months, which is much faster than the 60-month cycle from five years ago. Shorter design cycles place tremendous pressure on the system suppliers to quickly prototype and demonstrate their designs to original equipment manufacturers (OEMs). Designers and systems must be flexible to support emerging and changing consumer demands such as new multimedia interfaces that may not have been popular during design concept, but are a must-have feature at product launch. Flexibility is also required as new government mandates, such as new safety features, are introduced. OEMs are increasing their emphasis on new driver and passenger safety systems.This flexibility requirement often rules out many cell-based ASIC or ASSP implementations. Furthermore, to decrease R&D cost, automotive OEMs desire one base platform that can be scaled to include varying feature sets to differentiate between economical and luxury automobile models. There is also an ever growing number of automotive networking standards that need to be met. Finally, the growing demand for in-cabin multimedia and navigation is pushing DSP and graphics processing requirements beyond the limits of traditional DSP devices.
HardCopy III ASICs in wire bond packages are well suited for the automotive market in applications such as infotainment, GPS, fixed navigation, driver assist, and active safety functions. With the unique system development methodology enabled by the HardCopy design flow, the prototyping Stratix III FPGAs allow automotive products to be flexible up to the last minute to accommodate feature needs that are changing faster than typical automotive design cycles. The flexibility of Stratix III FPGAs enables you to create a single platform that you can use for multiple product lines. Once a product line is ready for production, you can quickly turn the design into a HardCopy III ASIC. Abundant multipliers and memory in HardCopy III ASICs and Stratix III FPGAs can be used to meet the growing appetite for high-quality video in infotainment and navigation features. The instant-on nature of ASICs and the extended temperature support of up to 125°C junction enable HardCopy III devices to meet stringent automotive system requirements. HardCopy ASICs have a long product life because of their co-existence with Altera's FPGA process nodes, which have a very solid history of long product life.
Contact your local sales representative to find out more about HardCopy III device availability in automotive grade.
Test and Measurement
With the rapidly increasing complexity in high-performance systems built for tomorrow’s applications, the ability to provide solutions that can test these products at full performance in a timely manner is imperative. Testing such solutions typically requires manipulating a large amount of data and monitoring many nodes in real-time, with low crosstalk and low interference between signals.
HardCopy III ASICs that are prototyped with Stratix III L FPGAs provide the required high I/O-to-logic ratio with I/O pins that support multiple standards, as well as high-speed memory interfaces to store the large amounts of data being processed.
Table 1 shows some applications using HardCopy III ASICs.
|Table 1. HardCopy III ASIC Applications|
|Tester Type||Applications Suitable for HardCopy III ASICs|
|Tabletop Testers||Display driver and DSP filtering of images for display|
|Wireless Network Testers||Baseband processing|
Commercial Avionics and Military
Commercial avionics and many military applications have stringent requirements for SEU tolerance. Standard cell ASICs provide good SEU tolerance, but their high development cost makes them prohibitive for these applications, as the cost must typically be amortized across medium to low volumes. HardCopy III ASICs provide excellent SEU tolerance and the lower total development costs of their FPGA-based design flow allow them to be used in a broader range of volumes and applications.