The HardCopy® III system development methodology enables you to seamlessly prototype HardCopy III ASICs using Stratix® III FPGAs at full system speed. In applications where you need higher performance, HardCopy III ASICs can provide up to twice the core logic performance over the FPGA prototype. The performance improvement is due to the following:
- Shorter routing due to much smaller die compared to FPGAs
- Fewer logic levels for certain combinatorial logic paths
- Flexibility in HCell macro placement
The performance advantage of HardCopy III ASICs is further enhanced with the ASIC-strength of the Quartus® II design software. You use SDC-formatted timing constraints to precisely define and analyze your timing requirements—one SDC for the ASIC and one SDC for the prototyping FPGA. You can also use physical synthesis and incremental compile features to further improve design performance. To take maximum advantage of this approach, Altera recommends that you use the HardCopy Device First approach in the Quartus® II software design flow.
Prototyping your system at reduced speed of the final silicon offers you tremendous verification benefits over simulation or traditional emulation. For example, when the clock for the HardCopy III ASIC device is targeted at 600 MHz, and the Stratix® III FPGA prototype is running at 300 MHz, there are close to 26 teracycles of emulation every 24-hour period, far surpassing other approaches.