HardCopy® III ASICs are architected to deliver low power that is comparable to standard cell ASICs. To achieve low current leakage, all unused blocks—RAMs, logic, global clocks, and PLLs—are removed from the power rail. The low dynamic power is a result of low routing capacitance because HardCopy III ASICs, similar to standard cell ASICs, use custom metal routing with exact wires and buffers.
HardCopy III ASICs typically deliver 50 percent or greater power reduction from the prototyping Stratix III® FPGA. The Stratix III architecture, Programmable Power Technology, and selectable core voltage breakthroughs enable the lowest possible power for high-end FPGAs in the same class.
Figure 1 shows the components of total power and looks at the relative values between the HardCopy III ASIC and the companion Stratix III FPGA prototype.
Figure 1. Stratix FPGA and HardCopy ASIC Power Comparison
Benefits of Low Power Consumption
Reducing the power consumption of custom logic devices carries far-reaching benefits for many applications, including:
- Space-constrained and other thermally challenging environments
- Price-sensitive applications where cooling systems are not cost effective
The HardCopy III family is just one example of Altera’s leadership in offering the lowest power custom logic devices. Combining a comprehensive approach of architecture and silicon enhancements, the latest semiconductor process technology, and complete power management tools for customers, Altera continues to deliver excellent power technology.
Quartus II Software Power Optimization
Design implementation details can improve performance, minimize area, and reduce power. Altera has taken a leadership position in bringing power optimization into the design flow. The Quartus® II software, combined with the architecture enhancements in HardCopy III ASICs, continues to deliver leadership power solutions.
Quartus II software has many transparent, automatic power optimizations that utilize the HardCopy III architecture details to minimize power, including:
- Transforming major functional blocks
- Mapping user RAMs so they use less power
- Restructuring logic to reduce dynamic power
- Reducing area and wiring demand for core logic to minimize dynamic power in routing
- Modifying placement to reduce clocking power
Accurate ASIC Power Estimation and Analysis
Altera supports power estimation and analysis from design concept through implementation with the Quartus II software's PowerPlay power analysis and optimization technology.
The PowerPlay early power estimator, used during the design concept phase, is a spreadsheet-based analysis tool that enables early power scoping based on device and package selection, operating conditions, and device utilization.
The PowerPlay power analyzer, used during the design implementation phase, is a far more detailed power analysis tool that uses actual design placement, routing, and logic configuration, and can use simulated waveforms to estimate dynamic power very accurately. The PowerPlay power analyzer, in aggregate, usually provides ±10 percent accuracy when used with accurate design information.