HardCopy® III ASICs are architected to deliver excellent single event upset (SEU) tolerance for your designs.
HardCopy III ASICs are built using an array of fine-grained HCell logic fabric. The HCells are configured and grouped together by via-programming to construct Stratix® III FPGA adaptive logic module (ALM) combinational and sequential logic functions, digital signal processing (DSP) blocks, and distributed MLAB memories.
The connections between HCells are hard-wired after via-programming. The high SEU tolerance nature of the HardCopy III ASICs is due not only to the hard-wiring, but also to the improved architecture of sequential elements. Contact your Altera® representative for details.
HardCopy III ASICs: Aligned for High-Reliability Systems
HardCopy III ASICs are well aligned for systems in high-performance and high-reliability computing, storage, military, and aerospace applications.
For the military and aerospace markets, the ability to provide high SEU immunity, low device power, and single-chip-instant-on make HardCopy III devices ideal for use in avionics, missiles, modems, sensors, radios, and unmanned vehicle applications.
HardCopy III ASICs support military temperature range -55°C to +125°C junction (pending silicon characterization) . Also, the HardCopy III ASIC design and manufacturing flows are compliant with the International Traffic in Arms Regulations (ITAR) established by the U.S. Department of State. This compliance allows designers of U.S. military electronics systems to take advantage of a secure HardCopy III design flow using the HardCopy system development methodology.
