Now available both with and without transceivers, HardCopy® IV ASICs are ideal for a wider application range than ever before.
The HardCopy IV (E, GX, and GT) ASIC variants, coupled with Altera’s complete system development methodology enabled by the Quartus® II development software, deliver the lowest risk, lowest total cost, fastest time-to-market, and fastest time-to-profit solution for many end markets and applications, including:
- Computer and Storage
- Test and Measurement
- Commercial Avionics and Military
The wireless end market is evolving at a rapid pace toward next-generation mobile broadband access systems such as WiMAX and 3GPP long-term evolution (LTE).
Wireless basestation applications for HardCopy IV ASICs include:
- Transceiver Interface
- Baseband Interface
- Power Amplification
- Control Processing
- Communication Interface
You not only benefit from the cost-effective, power-efficient, digital signal processing (DSP)-rich nature of the HardCopy IV ASICs used in your production system, but you also benefit in the development phase by using the Stratix® IV FPGA-based prototypes and having your wireless system in production quality before committing to the ASIC design handoff. For more information see Wireless Basestation Design.
The Stratix IV FPGA’s programmability is valuable when developing the intricate DSP functions required to send and receive the complex RF modulation needed to perform baseband generation, and to get the maximum efficiency from amplifiers and antennas. At such high rates, simulation is not effective in examining the effects of real-world noise and uncertainty. You can refine and test systems designed with FPGAs much more effectively than those designed with fixed approaches. DSP processors are flexible because code can be changed. However, even the fastest DSP processor is not as efficient as the Stratix and HardCopy devices because their abundant multipliers and registers allow you to implement DSP functions in parallel.
Wireline networks are evolving rapidly to support voice, video, and data delivery over the access network, with a converged multi-service network to aggregate and transport traffic. This high-volume market demands a low-cost custom logic solution in addition to a flexible development platform to deliver innovative access technologies solutions quickly. The dramatic growth of traffic being driven from these access networks also demands high-performance silicon and serial interface technologies.
Altera’s HardCopy IV ASICs (GX and GT) and Stratix IV FPGAs (GX and GT) are optimized for these high-end communications applications, with an emphasis on memory-rich and serial interface architectures. They are built to be interchangeable—the same high-speed transceivers, phase-locked loops (PLLs), I/Os, and memory blocks are employed in both the HardCopy ASIC and the prototyping FPGA. They also share compatible pinouts and packages. To design for a HardCopy ASIC-based access system, you use Stratix IV FPGAs (GX and GT) to quickly prototype your system at-speed with complete hardware and software design, verification, and bring up. You can even test-market your system with the FPGAs. When volume is justified, you hand off your design to Altera’s HardCopy Design Center for a quick ASIC implementation with guaranteed success.
Computer and Storage
Computer and storage are fast-moving markets. New products are introduced, sold, and replaced at a very fast pace. Being able to develop new products quickly using the HardCopy enabled system development methodology provides manufacturers with a significant competitive advantage. Further, with very short product life cycles in these markets, the HardCopy methodology enables companies to develop products very cost effectively.
Product differentiation is very important. However, with the development cost of cell-based ASICs sky-rocketing, manufacturers often feel that ASSPs are their only option. Using only ASSPs makes a product undifferentiated from competitors, limiting competition to cost only. HardCopy ASICs enable differentiating ASIC functionality in the moderate-volume, higher-end segments of the computing and storage markets. HardCopy ASICs are also ideal for ultra-high reliability applications such as mainframe computers because of their high single event upset (SEU) tolerance and low power requirements.
With the push towards high-resolution images and real-time diagnosis, the data transmission and image processing requirements in medical diagnostic equipment are becoming more and more sophisticated.
HardCopy IV ASICs that are prototyped with Stratix IV FPGAs provide the high performance DSP needed to collect, process, and display the data, the ability to transmit and receive data using high-speed LVDS differential interfaces, and the ability to buffer data using high-speed external memory interfaces.
The medical equipment industry requires clinical trials to test the operation of products. Because HardCopy IV ASICs and Stratix IV FPGAs are designed to be drop-in replacements to each other, you use the FPGA in the trials so that any changes in signal processing can be made quickly, and the design can complete the trials as quickly as possible. Once the medical product is approved and ready for production, you can implement the design in a pin- and package-compatible HardCopy ASIC.
Automotive applications for HardCopy IV ASICs include:
- Fixed Navigation
- Driver Assistance
- Active Safety Functions
Today a typical automotive design cycle is approximately 24 to 36 months. Shorter design cycles place tremendous pressure on the system suppliers to quickly prototype and demonstrate their designs to OEMs. Designers and systems must be flexible to support emerging and changing consumer demands such as new multimedia interfaces that may not have been popular during design concept, but are a must-have feature at product launch. Flexibility is also required as new government mandates, such as new safety features, are introduced. OEMs are increasing their emphasis on new driver and passenger safety systems. This flexibility requirement often rules out many cell-based ASIC or ASSP implementations. Furthermore, to decrease R&D cost, automotive OEMs desire one base platform that can be scaled to include varying feature sets to differentiate between economical and luxury automobile models. There are also a growing number of automotive networking standards that must be met. Finally, the growing demand for in-cabin multimedia and navigation is pushing DSP and graphics processing requirements beyond the limits of traditional DSP devices.
HardCopy IV E ASICs in wirebond packages are well suited for the automotive market. With the unique system development methodology enabled by the HardCopy design flow, the prototyping Stratix IV FPGAs allow automotive products to be flexible up to the last minute to accommodate feature needs that are changing faster than typical automotive design cycles. The flexibility of Stratix IV FPGAs enables you to create a single platform that you can use for multiple product lines. Once a product line is ready for production, you can quickly turn the design into a HardCopy IV ASIC. Abundant multipliers and memory in HardCopy IV ASICs and Stratix IV FPGAs can be used to meet the growing appetite for high-quality video in infotainment and navigation features. The instant-on nature of ASICs and the extended temperature support of up to 125°C junction (pending characterization) enable HardCopy IV devices to meet stringent automotive system requirements. HardCopy ASICs have a long product life because of their co-existence with Altera's FPGA process nodes, which have a very solid history of long product life.
Test and Measurement
With the rapidly increasing complexity in high-performance systems built for tomorrow’s applications, the ability to provide solutions that can test these products at full performance in a timely manner is imperative. Testing such solutions typically requires manipulating a large amount of data and monitoring many nodes in real-time, with low crosstalk and low interference between signals.
HardCopy IV ASICs that are prototyped with Stratix IV FPGAs provide the required high I/O-to-logic ratio with I/O pins that support multiple standards, as well as high-speed memory interfaces to store the large amounts of data being processed.
Table 1 shows some applications suitable for HardCopy IV ASICs.
|Table 1. HardCopy IV ASIC Applications|
|Tester Type||Applications Suitable for HardCopy IV ASICs|
|Wireless Network Testers||
Commercial Avionics and Military
Commercial avionics and many military applications have stringent requirements for SEU tolerance. Standard cell ASICs provide good SEU tolerance, but their high development cost makes them prohibitive for these applications, as the cost must typically be amortized across medium to low volumes. HardCopy IV ASICs provide excellent SEU tolerance and the lower total development costs of their FPGA-based design flow allow them to be used in a broader range of volumes and applications.