HardCopy® ASIC system development methodology enables you to seamlessly prototype HardCopy IV ASICs using the high-performance Stratix® IV FPGAs at full system speed. HardCopy IV ASICs can provide up to twice the core logic performance over the FPGA prototype device.
The performance improvement is due to:
- Shorter routing using a much smaller die compared to the FPGA
- Fewer logic levels for certain combinatorial logic paths
- Flexibility in HCell macro placement
The performance advantage of HardCopy IV ASICs is further enhanced with the ASIC-strength of the Quartus® II design software. You use synopsys design constraint (SDC)-formatted timing constraints to precisely define and analyze your timing requirements—one SDC for the ASIC and one SDC for the prototyping FPGA. You can also use physical synthesis and incremental compile features to further improve design performance.
Prototyping your system at reduced speed of the final silicon still offers you tremendous verification benefit over simulation or traditional emulation approaches.
For example, when the clock for the HardCopy IV ASIC is targeted at 600 MHz, and the Stratix IV FPGA prototype is running at 300 MHz, there are close to 26 teracycles of emulation every 24-hour period—far surpassing other simulation or emulation approaches.