HardCopy® IV ASICs are architected to deliver excellent single event upset (SEU) tolerance for your designs.
HardCopy IV ASICs are built using an array of fine-grained HCell logic fabric. HCells are configured and grouped together by via-programming to construct Stratix® IV FPGA adaptive logic module (ALM) combinational and sequential logic functions, digital signal processing (DSP) blocks, and distributed MLAB memories.
The connections between HCells are hard-wired after via-programming. The high SEU tolerance nature of the HardCopy IV ASICs is due not only to the hard-wiring, but also to improved architecture of sequential elements. Contact your Altera® representative for details.
Aligned for High-Reliability Systems
HardCopy IV ASICs are well aligned for systems in high-performance, high-reliability computing, storage, military, and aerospace applications.
For the military and aerospace markets, the ability to provide high SEU immunity, low device power, and single-chip-instant-on make HardCopy IV devices ideal for use in avionics, missiles, modems, sensors, radios, and unmanned vehicle applications.
The HardCopy IV ASIC design and manufacturing flow are compliant with the International Traffic in Arms Regulations (ITAR) established by the U.S. Department of State. This compliance allows designers of U.S. military electronics systems to take advantage of a secure HardCopy IV design flow using the HardCopy system development methodology.