HardCopy® IV ASICs (GX) and Stratix® IV FPGAs (GX and GT) with embedded transceivers deliver breakthrough levels of system bandwidth and power efficiency for high-end applications, allowing you to innovate without compromise. The transceivers are based on 40-nm technology and include a number of features to ensure excellent jitter performance combined with superior signal integrity for both backplane and chip-to-chip applications. HardCopy IV ASIC (GX) and Stratix IV FPGA (GX and GT) transceivers build on the success of previous generation Altera® devices with transceivers, and include several digital blocks you can configure to simplify the implementation and support of emerging standards and proprietary serial protocols.
Key HardCopy ASIC Transceiver Features
- Up to 24 transceivers supporting 600 MHz to 10.3 Gbps
- Up to an additional 12 transceivers supporting 600 MHz to 6.5 Gbps
- Dynamically programmable differential output voltage (VOD) and pre-emphasis settings for improved signal integrity
- User-controlled or adaptive 4-stage receiver equalization with up to 17 dB of gain to compensate for frequency-dependent losses in the physical medium
- Support for CDR-based serial standards including but not limited to: PCI Express® (PCIe®) Gen1 and Gen2, Serial RapidIO®, Gigabit Ethernet (GbE), XAUI/HiGig, the Optical Internetworking Forum (OIF) CEI-6G, Interlaken, SFI-5, GPON, 10G EPON/GPON, SONET, CPRI, OBSAI, Fibre Channel, HyperTransportTM, SDI, XFI, and Altera’s SerialLite II
- Support for single-wide and double-wide basic modes to implement custom protocols
- Individual transmitter and receiver power-down to reduce power consumption during non-operation
- Selectable on-chip termination resistors for improved signal integrity on a variety of transmission media
- Transceiver-to-core interface supports selectable 8-, 10-, 16-, 20-, 32-, and 40-bit-wide data transfer
- Receiver loss-of-signal indicator
- Built-in self test (BIST)
- Plug & Play Signal Integrity with hot insertion/removal protection circuitry
- Dynamic reconfiguration of the transceiver to support multiple protocols and data rates on the same channel
- Two phase-locked loop (PLL) inputs and independent clock dividers on each transmitter to allow different clock rates for each channel
- Generic polarity inversion for basic modes and polarity inversion specifically for PCIe
- Rate matcher, pattern detector, and word aligner with programmable patterns
- Dedicated circuitry compliant with the physical interface for PCI Express (PIPE), XAUI, and GbE
- PIPE interface connects directly to embedded PCIe Gen1 (2.5 Gbps) and Gen2 (5.0 Gbps) hard intellectual property (IP) or to soft IP
- Built-in byte ordering so that a frame or packet always starts in a known byte lane
- 8B/10B encoder/decoder performs 8-bit to 10-bit encoding and 10-bit to 8-bit decoding
- Receiver rate-matching FIFO buffer resynchronizes the received data with the local reference clock
- Phase compensation FIFO buffer performs clock domain translation between the transceiver block and the logic array
Block Diagram
Figure 1 shows the block diagram of the Stratix IV FPGA (GX and GT) and HardCopy IV ASIC (GX) transceivers, both physical medium attachment (PMA) and physical coding sublayer (PCS). The blocks within the PCS can be bypassed, depending on your requirements.
Figure 1. HardCopy IV (GX) and Stratix IV (GX and GT) Transceivers, PMA, and PCS Block Diagram
HardCopy IV GX transceivers include dedicated circuitry to implement standard and proprietary protocols operating between 600 Mbps and 6.5 Gbps. The transceivers are also capable of supporting data rates as low as 270 Mbps using oversampling, which is important when supporting legacy protocols and protocols with multiple data rates. When augmented with Altera IP, HardCopy IV ASIC (GX) and Stratix IV FPGA (GX and GT) transceivers provide a complete, low-risk solution for serial protocol implementation.
