With its mix of low price, low power, and features, Altera's MAX® V CPLDs deliver the market's best value. Featuring a non-volatile architecture and one of the CPLD industry's largest density devices, the MAX V family provides robust new features at up to 50 percent lower total power compared to competing CPLDs.
- MAX V CPLD family
- Package and I/O offering
- Speed and temperature grade offering
- Features and benefits
MAX V devices are ideal for general-purpose and power- and space-constrained designs in many market segments, including wireline, wireless, industrial, consumer, computer and storage, broadcast, and military. MAX V CPLDs are used for a wide variety of applications previously implemented in older generation ASICs, ASSPs, FPGAs, and discrete logic devices.
Table 1 outlines the MAX V device family members and features.
| Table 1. MAX V CPLD Family Overview | |||||||
| Feature | 5M40Z | 5M80Z | 5M160Z | 5M240Z | 5M570Z | 5M1270Z | 5M2210Z |
|---|---|---|---|---|---|---|---|
| Logic elements (LEs) | 40 | 80 | 160 | 240 | 570 | 1,270 | 2,210 |
| Equivalent macrocells | 32 | 64 | 128 | 192 | 440 | 980 | 1,700 |
| User flash memory (bits) | 8,192 | 8,192 | 8,192 | 8,192 | 8,192 | 8,192 | 8,192 |
| Global clocks and control pins | 4 | 4 | 4 | 4 | 4 | 4 | 4 |
| Internal oscillator | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
| Digital phase-locked loop (PLL) (1) | Yes | Yes | Yes | Yes | Yes | Yes | Yes |
| Maximum user I/O pins | 54 | 79 | 79 | 114 | 159 | 271 | 271 |
| Availability | Buy Now | Buy Now | Buy Now | Buy Now | Buy Now | Buy Now | Buy Now |
- Digital PLL is an optional intellectual property (IP) that can be instantiated into unused LEs.
Table 2 shows an overview of MAX V CPLD packaging options and associated available number of user I/Os.
| Table 2. MAX V CPLD Package and Maximum User I/O Pins (1) | |||||||
| Package Size | 5M40Z | 5M80Z | 5M160Z | 5M240Z | 5M570Z | 5M1270Z | 5M2210Z |
|---|---|---|---|---|---|---|---|
| 64-pin Micro FineLine BGA (MBGA) (4.5 mm x 4.5 mm) (2) |
30 | 30 | - | - | - | - | - |
| 64-pin plastic enhanced quad flat pack (QFP) (7 mm x 7 mm) |
54 | 54 | 54 | - | - | - | - |
| 68-pin MBGA (5 mm x 5 mm) (2) |
- | 52 | 52 | 52 | - | - | - |
| 100-pin thin QFP (14 mm x 14 mm) | - | 79 | 79 | 79 | 74 | - | - |
| 100-pin MBGA (6 mm x 6 mm) (2) |
- | - | 79 | 79 | 74 | - | - |
| 144-pin QFP (20 mm x 20 mm) | - | - | - | 114 | 114 | 114 | - |
| 256-pin FineLine BGA (FBGA) (17 mm x 17 mm) (3) |
- | - | - | - | 159 | 211 | 203 |
| 324-pin FBGA (19 mm x 19 mm) (3) |
- | - | - | - | - | 271 | 271 |
- All packages support migration across densities
- BGA with 0.5-mm pitch
- BGA with 1.0-mm pitch
MAX V devices support 1.8 V on their VCCINT pins. This external supply powers the device core directly, providing functionality with low dynamic and low stand-by power. The MultiVolt I/O interface (VCCIO) provides flexible support for many I/O standards using 1.2-V, 1.5-V, 1.8-V, 2.5-V, and 3.3-V voltage levels.
Table 3 shows the available MAX V CPLD speed and temperature grade options.
| Table 3. MAX V Speed and Temperature Grade Offering | ||||
| Device | Speed Grade | |||
|---|---|---|---|---|
| -4 Commercial | -5 Commercial | -5 Industrial | Automotive (1) | |
| 5M40Z |  |
|
|
C.F. |
| 5M80Z | |
|
|
C.F. |
| 5M160Z | |
|
|
C.F. |
| 5M240Z | |
|
|
C.F. |
| 5M570Z | |
|
|
C.F |
| 5M1270Z | |
|
|
C.F. |
| 5M2210Z | |
|
|
C.F. |
- Contact your nearest Altera® representative for automotive grade availability and support.
Features
MAX V CPLDs offer features (see Table 4) that directly translate to designer benefits, including lower total cost, design ease of use, and system integration.
| Table 4. MAX V CPLD Features at a Glance | |
| Feature | Description |
|---|---|
| Cost optimized | MAX V CPLDs are manufactured using a low-cost 0.18-µm fab process combined with the latest low-cost packaging technologies. |
| Low power | MAX V CPLDs offer up to 50 percent lower total power compared to equivalent density competitive CPLDs, generating less heat and saving battery power. |
| Internal oscillator | MAX V CPLDs offer an internal oscillator which can replace external discrete timing devices for use as a simple clocking source, saving BOM costs. |
| Fast power-on and reset | MAX V CPLDs power on and reset themselves quickly (500 µs or less), making them ideal for power management, power sequencing, and monitoring of other devices on the PCB. |
| Realtime in-system programmability (ISP) | MAX V CPLDs allow you to update a second configuration image while the CPLD is in operation. |
| I/O capabilities | MAX V I/Os are hot-socket compliant and support LVTTL, LVCMOS, PCITM, and LVDS output interface standards, along with other bus-friendly options (e.g. output enable per pin, Schmitt triggers, slew rate control, and others). |
| Green packages | All packages (EQFP, TQFP, MBGA, and FBGA) are available in restriction of hazardeous substances (RoHS)-compliant variants, meeting the "low-halogen" requirements per JEDEC document JED 709 (draft). Selected packages are available in leaded variants. (1), (2), (3), (4) |
| Parallel Flash Loader | MAX V CPLDs feature a JTAG block that can configure external non-JTAG-compliant devices such as discrete flash memory devices using the Parallel Flash Loader IP Megafunction. |
| Industrial temperature support | MAX V CPLDs support the industrial temperature range, -40°C to +100°C (junction), required for various industrial and other temperature-sensitive applications. |
- Plastic enhanced quad flat pack (EQFP)
- Thin quad flat pack (TQFP)
- FBGA
- MBGA
