The MAX® II CPLD architecture has two unique features not found in other CPLD architectures: an internal oscillator and 8 Kbits of non-volatile user flash memory (refer to Figure 1). You can benefit from these two unique features by:
- Using them instead of external components to save PCB area and cost
- Using the oscillator to automatically start and stop the device
- Using the user flash memory to store system parameters and product information
Figure 1. User Flash Memory Block and Oscillator
The internal oscillator is a 4.4-MHz (typical output) clock source and resides inside the user flash memory block. Not only does the internal oscillator reduce component count, it can also be used to reduce system power. For example, many industrial and consumer applications, such as portable media players, do not require the CPLD to be powered on all the time. In these applications, it is preferred to have a design in which the CPLD remains off most of the time and only powers on when needed. Altera® MAX II CPLDs are well suited for such applications because:
- The internal oscillator can be used to automatically turn the device on and off, with no system intervention.
- When the CPLD is off, the only current consumption is the leakage current due to active inputs (IDK). This current draw is negligible (10 µA), compared to traditional macrocell-based CPLDs, which draw greater than a milliamp.
- Robust power sequencing allows MAX II CPLDs to power on and off, without adversely affecting the system.
You can find technical information about the oscillator in the Using User Flash Memory in MAX II Devices (PDF) chapter of the MAX II Device Handbook and the altufm_osc megafunction available within the Quartus® II software.
See the following for more information about oscillator applications:
- AN 491: Auto Start Using MAX II CPLDs (PDF)
- AN 496: Using the Internal Oscillator in MAX II CPLDs (PDF)
- AN 501: Pulse Width Modulator Using MAX II CPLDs (PDF)
- EDN Article—Calibrate the Internal Oscillator to +/-0.3% (or better) with an External Clock
The user flash memory is an 8-Kbit user-accessible and programmable block of non-volatile flash memory that stores user-defined data, such as a serial EEPROM. The user flash memory block is accessible by any logic element (LE) within the MAX II CPLD. The user flash memory block offers the following features:
- Interface to the CPLDs logic array or JTAG circuit
- Non-volatile storage, 16-bit wide and 8,192 total bits
- Partitioned as two sectors for independent sector erase, reads, or writes
- Built-in oscillator that optionally drives the CPLD logic array
- Optional auto-increment addressing
- Serial interface to logic array, programmable with a Quartus II automated GUI. Several industry standard protocol options are available:
- None (defaults to Altera Serial Interface)
Commonly used applications include using the user flash memory to store the following information: encryption keys, PCB serialization numbers, firmware revision numbers, or initialization code to boot ASICs, ASSPs, analog components, microprocessors, or microcontrollers.
You can find technical information about the user flash memory in the Using User Flash Memory in MAX II Devices (PDF) chapter of the MAX II Device Handbook. The user flash memory interfaces with the JTAG circuitry and with the core logic, giving you the flexibility to write to the device in a variety of ways. For example, if you wish to interface to a standard bus such as serial peripheral interface (SPI), I2C, parallel, etc., the Quartus II software automates the interface through a GUI-based megafunction.