The MAX® II CPLD family is a non-volatile, instant-on programmable logic family using an industry-first CPLD architecture that allows you to reduce system power, space, and cost.
- Package and I/O Offering
- Speed Grade Offering
- Industrial Temperature Support
- Questions and Answers
The foundation of lower system cost and power savings is an architecture combining all of the advantages of Altera's MAX II CPLDs, while leveraging Altera's expertise in FPGA products and look-up table (LUT)-based architectures. The LUT-based architecture delivers the maximum logic capability in the smallest I/O pad-constrained space.
MAX II CPLDs are used for a wide variety of applications previously implemented in older generation FPGAs, ASSPs, and standard-logic devices.
Table 1 outlines the MAX II device family members and features.
|Table 1. MAX II CPLD Family Overview|
|Logic Elements (LEs)||240||570||1,270||2,210|
|Maximum User I/O Pins||80||160||212||272|
|User Flash Memory (Kbits)||8||8||8||8|
|Availability||Buy Now||Buy Now|
- All MAX IIZ CPLDs are available to order and released for shipments, but lead-times might be six to ten weeks. Please contact your local Altera sales representative to help expedite your order.
Based on a cost- and quality-optimized 0.18-µm six-layer metal flash process, the MAX II CPLD family is targeted for general-purpose, low-density logic applications, such as mobile handsets and smart phones. MAX II CPLDs are ideal for interface bridging, I/O expansion, device configuration, and power-up sequencing. Pre-built and hardware-verified design examples are available to get you started on your next design. Table 2 shows an overview of MAX II CPLD packaging and I/O pin counts.
|Table 2. MAX II CPLD Package and Maximum User I/O Pins (1)|
|68-Pin Micro FineLine BGA
(5 mm x 5 mm) (2), (3)
|100-Pin Micro FineLine BGA
(6 mm x 6 mm) (2), (3)
|100-Pin FineLine BGA
(11 mm x 11 mm) (2), (4)
|100-Pin Thin-Quad Flat Pack (TQFP)
(16 mm x 16 mm)
|144-Pin Micro FineLine BGA
(7 mm x 7 mm) (2)
(22 mm x 22 mm)
|256-Pin Micro FineLine BGA
(11 mm x 11 mm) (2)
|256-Pin FineLine BGA
(17 mm x 17 mm)
|324-Pin FineLine BGA
(19 mm x 19 mm)
- All packages support migration across densities.
- Packages only available in RoHS-compliant versions.
- BGA: ball-grid array with 0.5-mm pitch.
- BGA with 1.0-mm pitch.
Table 3 shows the available MAX II CPLD speed grades.
|Table 3. MAX II Speed Grade Offering|
Table 4 shows industrial temperature support for MAX II devices.
The low-cost MAX II CPLDs offer architectural and board management features (see Table 5) to optimize ease of use and system integration.
|Table 5. MAX II CPLD Features at a Glance|
|Cost-Optimized Architecture||Altera® MAX II CPLDs have a new CPLD architecture that breaks through traditional macrocell power, space, and cost limitations.|
|Low Power||MAX II CPLDs offer the lowest dynamic power in the CPLD industry with one-tenth the power of previous MAX CPLDs.|
|Features Unique to MAX II CPLDs||MAX II CPLDs offer 8 Kbits of user-accessible flash memory to implement on-chip serial or parallel non-volatile storage.|
|Real-Time In-System Programmability (ISP)||MAX II CPLDs allow you to update the configuration flash memory while the CPLD is in operation.|
|I/O Capabilities||MAX II CPLDs support a variety of single-ended I/O interface standards such as LVTTL, LVCMOS, and PCI.|
|Packages Available||TQFP, 1.0-mm pitch FBGA, and 0.5-mm pitch MBGA. (1), (2), (3)|
|Parallel Flash Loader||MAX II CPLDs feature a JTAG block that can configure external non-JTAG-compliant devices such as discrete flash memory devices using the Parallel Flash Loader megafunction.|
|Industrial Temperature Support||MAX II CPLDs support the industrial temperature range, -40°C to +100°C (junction), required for various industrial and other temperature-sensitive applications.|
|Extended Temperature Support||MAX II CPLDs are offered in the extended temperature range, -40°C to +125°C (junction), to support automotive and other temperature-sensitive applications.|