Challenges
New wireless standards such as 3G and Long Term Evolution (LTE) are increasing digital signal processing (DSP) needs while adding pressure to reduce overall system costs. Operating and maintenance costs of equipment often placed in remote locations drive stringent energy consumption requirements. Although equipment is often placed in thermally challenging environments, active cooling solutions such as fans are not allowed because of reliability concerns.
Solution
Altera understands the unique challenges facing wireless infrastructure systems designers. Arria® II FPGAs deliver the processing bandwidth, predictable latency, low power, and flexibility required for emerging wireless infrastructure designs. Innovative transceiver features, coupled with a suite of reference designs and development kits, accelerate wireless systems design.
Table 1 highlights the advantages Arria II FPGAs provide for wireless system applications.
| Table 1. Key Wireless System Application Advantages of Arria II FPGAs | |
| Feature | Advantage |
|---|---|
| 6.375-Gbps Transceivers with Predictable Latency | Support CPRI and OBSAI line rates up to 6.144 Gbps with deterministic latency required by both the CPRI and OBSAI specifications |
| Low Power | For 6G applications, Arria II FPGAs are the lowest power FPGA and offer up to 20 percent lower total power than competing solutions |
| Abundant Memory at Every Density | Up to 16.4 Mbits of on-chip memory |
| DSP Blocks | Advanced DSP blocks including up to 1,040 embedded 18-bit x 18-bit multipliers to process DSP-intensive algorithms |
| Nios® II Embedded Soft Processor | The world’s most versatile embedded soft processor, ideal for Ethernet packet processing or updating digital predistortion (DPD) coefficients in wireless systems |
| Industrial Temperature Support | Support for harsh operating environments from -40°C to 100°C. |
Typical Remote Radio Head Implementation
With channel bandwidth increasing up to 20 MHz and the requirement for multiple sector, multiple antenna multiple-input multiple-output (MIMO) configurations, implementation of RF card functions requires a high-performance, power-efficient scalable silicon platform. Sample rate converter (SRC) blocks such as digital upconverter (DUC), digital downconverter (DDC), crest-factor reduction (CFR), and DPD blocks can be implemented efficiently on FPGAs.
Figure 1 shows an Arria II GX FPGA-based implementation that not only cost-effectively addresses the processing requirements, but also provides a measure of future-proofing via support for in-field programmability.
Figure 1. FPGA-Based Implementation of RF Card Functionality
Notes:
- O&M = operation and maintenance
- CPRI = Common Public Radio Interface
- OBSAI = Open Base Station Standard Initiative
Resources
| Table 2. Design Resources | ||
| Category | Resource | Description |
|---|---|---|
| Development Kit Resources | ||
 |
Arria II Development Kits | Altera and partners are developing a portfolio of development kits to jump-start Arria II FPGA designs. Each kit comes with everything you need to evaluate and design with Arria II FPGAs. |
| Software and IP Resources | ||
 |
DSP Builder | Altera’s DSP Builder technology allows you to go from system definition/simulation using the industry-standard The MathWorks/Simulink tools to FPGA system implementation in a matter of minutes. |
| CPRI IP | Radiocomp CPRI intellectual property (IP) cores enable the quick and flexible deployment of both REC (radio equipment controller) and RE (radio equipment) interfaces. | |
| OBSAI IP | Radiocomp OBSAI IP enables the quick and flexible deployment of both base transceiver station and RRH (remote radio head) interfaces. | |
| Nios II Embedded Processor | The world's most versatile processor supported by easy-to-use development tools and a portfolio of FPGA development kits. | |
| Memory Controllers | Memory controller IP from Altera and partners for DDR, DDR2, DDR3 and other popular external memory device interfaces. | |
| AMPPSM Partners | Altera Megafunction Partner Program (AMPP) partners offering IP and development solutions for wireless infrastructure applications. | |
| Application Notes and Reference Designs | ||
 |
Crest Factor Reduction | Demonstrates how CFR algorithms for OFDM systems can be efficiently implemented in Altera® FPGAs. |
| AN 544: Digital IF Modem Design with the DSP Builder Advanced Blockset (PDF) | Describes designing a DUC in the transmitter and a DDC for radio frequency (RF) cards and remote radio head applications. | |
