Arria® V FPGAs balance cost and performance while delivering the lowest total power for mid-range applications, such as remote radio units, 10G/40G line cards, and broadcast studio equipment. There are four targeted variants, including SoC FPGA variants with an ARM-based hard processor system (HPS):
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SoC FPGAs – Your Customizable ARM Processor-Based SoC
SoC FPGAs let you reduce system power, system cost, and board space by integrating a HPS – consisting of processors, peripherals, and memory controller – with the FPGA fabric using a high-bandwidth interconnect backbone. The combination of the HPS with Altera's 28-nm low-power FPGA fabric provide the performance and ecosystem of an applications-class ARM® processor with the flexibility and digital signal processing (DSP) richness of the Arria V FPGAs.
Industry-Leading Low Power
The device family is developed on TSMC's 28-nm Low-Power (28LP) process, which contributes to their optimized balance of cost, performance, and industry-leading low power:
- Lowest static power of any mid-range FPGA (<800 mW at 500K logic elements)
- Lowest power serial transceivers (<100-mW maximum power consumption per channel at 6.375 Gbps and <140-mW maximum power consumption per channel at 10.3125 Gbps) in a mid-range FPGA
- Up to 40 percent lower total power compared with 6.375-Gbps Arria II FPGAs
- Over 4,000 MIPS (Dhrystones 2.1 benchmark) processing performance for under 1.8 W (for SoC FPGA)
- Hardened intellectual property (IP) for memory interfaces, processors, and the PCI Express® standard further reduces total power
Abundant Hard IP Blocks
The device family's architecture integrates an abundance of hard IP blocks, including the following:
- Hard memory controllers
- PCI Express Gen2 x4 with multifunction support
- Variable-precision DSP blocks optimized for finite impulse response (FIR) filters
- HPS (for SoC FPGAs):
- Dual-core ARM CortexTM-A9 MPCoreTM processor
- Embedded peripherals (Ethernet, USB, flash memory, and more)
- High bandwidth (>125 Gbps) HPS-FPGA interconnect
With ready-to-use functions, these hard IP blocks consume less power, ease your design process, and provide you with more logic resources for developing differentiated product features compared to soft logic implementations. To protect your valuable IP investments, Arria V FPGAs also provide comprehensive design protection, with features including 256-bit Advanced Encryption Standard with volatile and non-volatile keys.
The hard IP functions, along with features including integrated 10.3125-Gbps transceivers, make Arria V FPGAs ideal for meeting the performance and changing standards requirements of mid-range applications in the wireless, wireline, broadcast, and video end markets.
Get a Complete Solution
Arria V FPGAs are backed by soft IP cores, design guidelines, and collateral to help you design with ease in several market segments.
