Arria® V family of FPGAs offer the highest bandwidth and deliver the lowest total power for midrange applications, such as remote radio units, 10G/40G line cards, and broadcast studio equipment. There are five targeted variants, including SoC variants with a dual core ARM® CortexTM-A9 hard processor system (HPS) to best meet your performance, power, and integration needs.
Table 1. Arria V FPGA Family Variants
| Variant | Description |
|---|---|
| Arria V GZ FPGA | Highest bandwidth midrange FPGA wth up to 36 backplane-capable 12.5 Gbps transceivers. |
| Arria V GT FPGA | Lowest power midrange FPGA for applications that require up to 20 transceivers at 10.3125 Gbps and SFF 8431 compliance |
| Arria V GX FPGA | Lowest power midrange FPGA for applications that require up to 32 backplane-capable 6.5536 Gbps transceivers |
| Arria V ST SoC | SoC with ARM-based HPS and 10.3125 Gbps transceivers |
| Arria V SX SoC | SoC with ARM-based HPS and 6.5536 Gbps backplane-capable transceivers |
See Arria V FPGAs Running:
|
High Bandwidth Interfaces on Arria V GZ: Featuring PCIe® Gen3 Hard IP |
High Bandwidth Interfaces on Arria V GZ: Featuring 1600 Mbps DDR3 Memory |
|
Arria V GX FPGAs 6.375 Gbps CEI Backplane Driving Capability |
Arria V GT FPGA 10.3125 Gpbs for SFF8431 Applications |
Arria V FPGA variants offer a number of solutions to meet the bandwidth requirements of you application while balancing your power and cost targets.
Table 2. Comparison of Arria V FPGA Variants
| Feature | Arria V GZ FPGA | Arria V GT FPGA | Arria V GX FPGA | Arria V ST SoC | Arria V SX SoC |
|---|---|---|---|---|---|
| ALMs (K) | 170 | 190 | 190 | 174 | 174 |
| Variable-Precision DSP | 1,139 | 1,156 | 1,156 | 1,068 | 1,068 |
| M20K Blocks | 1,700 | - | - | - | - |
| M10K Blocks | - | 2,414 | 2,414 | 2,282 | 2,282 |
| DDR3 Memory Interface Speed | 800 MHz | 667 MHz | 667 MHz | 667 MHz | 667 MHz |
| Hard Memory Controllers | - | 4 | 4 | 4 | 4 |
| Transceivers (Gbps) | 12.5 Gbps | 10.3125 | 6.5536 | 10.3125 | 6.5536 |
| PCI Express® (PCIe) Gen3/2/1 HIP | 1 | - | - | - | - |
| PCIe Gen2/1 HIP | - | 2 | 2 | 2 | 2 |
| Design Security |  |
|
|
|
|
| SEU Mitigation | |
|
|
|
|
Figure 1: Architecture of Arria V FPGAs
Industry's Lowest Power
Arria V GZ FPGAs offer the lowest power-per-bandwidth for midrange applications, and are ideal for power-sensitive designs that require transceivers up to 12.5 Gbps. At 10G data rates, Arria V GZ FPGAs consume less than 180 mW per channel and at 12.5 Gbps consume less than 200 mW per channel. Arria V GZ FPGAs also offer a lower static power offering with a -3L speed grade.
Arria V GX and GT FPGAs offer the lowest total power for mid-range applications by using the 28 nm low power process to deliver the lowest static power, offering the lowest power transceivers for speeds up to 10.3125 Gbps, and providing superior fabric with hard IP designed to lower dynamic power. Arria V devices provide a 40% on average power reduction compared to the previous generation of mid-range FPGAs.
Customizable ARM Processor-Based SoCs
Altera SoCs let you reduce system power, system cost, and board space by integrating a HPS – consisting of processors, peripherals, and memory controller – with the FPGA fabric using a high-bandwidth interconnect backbone. The combination of the HPS with Altera's 28 nm low-power FPGA fabric provide the performance and ecosystem of an applications-class ARM processor with the flexibility and digital signal processing (DSP) richness of the Arria V FPGAs.
HPS (for SoCs)
Dual-core ARM Cortex-A9 MPCoreTM processor
