Arria V FPGA Family Overview

The 28 nm Arria^® V FPGA family offers the lowest power, highest bandwidth FPGAs for mid-range applications, such as remote radio units, 10G/40G line cards, and in-studio mixers. A comprehensive offering of five device variants allows designers to optimally choose a solution that meets their price, performance, and power requirements. See the tables below for an overview of the Arria V FPGA and SoC FPGA family and package choices.

• Arria V GX FPGA with up to 6.5536 Gbps transceivers 
• Arria V GT FPGA with up to 10.3125 Gbps transceivers 
• Arria V GZ FPGA with up to 12.5 Gbps transceivers
• Arria V SX SoC FPGA with ARM-based hard processor system (HPS) and 6.5536 Gbps transceivers 
• Arria V ST SoC FPGA with ARM-based HPS and up to 10.3125 Gbps transceivers 

Table 1. Arria V GX FPGA Family Overview (1) 

Notes:

1. Arria V GX devices are offered in -3, -4, -5, and -6 speed grades.

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Table 2. Arria V GX FPGA Package Overview and User I/O Pins (I/O Pins, Transceivers)

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Table 3. Arria V GT FPGA Family Overview (1)

Notes:

1. Arria V GT devices are offered in the -5 and -3 speed grades.
2. 10 Gbps transceivers are for chip-to-chip connections only.
3. Each set of three 6.5536 Gbps transceivers can be configured as two 10.3125 Gbps transceivers with the exception of one set in the F672 package and two sets in all other packages which have a maximum rate of 6.5536 Gbps.

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Table 4. Arria V GT FPGA Package Overview and User I/O Pins (I/O Pins, Maximum 6 Gbps Transceivers, Maximum 10 Gbps Transceivers) (1) (2)

Notes:

1. Pin migration within each package.
2. Each set of three 6.5536 Gbps transceivers can be configured as two 10.3125 Gbps transceivers with the exception of one set in the F672 package and two sets in all other packages which have a maximum rate of 6.5536 Gbps.

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Table 5. Arria V GZ FPGA Family Overview

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Table 6. Arria V GZ FPGA Package Overview, Transceivers and User IO Pins

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Table 7. Arria V SX SoC FPGA Family Overview

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Table 8. Arria V SX SoC FPGA Package Overview and User I/O Pins (FPGA IO, HPS I/O Pins Transceivers)

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Table 9. Arria V ST SoC FPGA Family Overview

Notes:

1. 10 Gbps transceivers are for chip-to-chip connections only.
2. Each set of three 6.375 Gbps transceivers can be configured as two 10 Gbps transceivers with the exception of the two sets nearest the PCIe hard IP which have a maximum rate of 6.375 Gbps.

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Table 10. Arria V ST SoC FPGA Package Overview and User I/O Pins (I/Os Pins, Transceivers)

Note:

1. Each set of three 6.375 Gbps transceivers can be configured as two 10 Gbps transceivers with the exception of the two sets nearest the PCIe hard IP which have a maximum rate of 6.375 Gbps.

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Table 11. Temperature Support

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Related Links

• Overview for the Arria V Device Family (PDF)
• 28 nm device portfolio page
• Arria V and Cyclone^® V FPGA variable-precision DSP block architecture page

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