Altera’s Arria® V FPGAs deliver the lowest power solution for applications requiring high performance and up to 10.3125-Gbps transceivers. Arria V FPGAs achieve this leadership position with the 28-nm Low-Power (28LP) process technology, lower gate capacitance, a power-optimized transceiver architecture, and an increased amount of hard intellectual property (IP). This combination results in an FPGA family that is both affordable, with high performance, at the lowest power.
Estimate your power consumption now:
- Arria II GX, Arria II GZ, and Arria V PowerPlay early power estimator on the PowerPlay Early Power Estimators (EPE) and Power Analyzer web page
- Arria V Device Handbook (PDF)
- Arria V Pin Connection Guidelines (PDF)
- Test drive the Arria V EPE and enter for a chance to win
Lowest Total Power in the Mid Range
Arria V FPGAs leverage the 28LP process to offer the lowest static power, generations of integrated transceiver experience, and a superior fabric designed to lower dynamic power, all tuned to the needs of the mid-range market. This results in an ideal balance of power, performance, and price for mid-range applications. Compared to Xilinx’s Kintex-7 and Virtex-7 FPGAs – even their lowest power 0.9-V offerings – Arria V FPGAs provide lower total power, the lowest static power, and the lowest transceiver power. The only exception to this leadership is in designs with high I/O counts and low transceiver counts, which would be better served with our absolute lowest power FPGA family, the Cyclone® V FPGA.
The examples shown in Figure 1 model power for real designs at 85C junction temperature in Arria V FPGAs and Xilinx 7-Series FPGAs. As shown in the comparisons, Arria V FPGAs consume the lowest total power, even compared to 0.9-V devices (indicated by the "-2L" in the part number). The Arria V FPGA PowerPlay EPE spreadsheets are used to estimate power for all of the examples below, and can be found on the Arria V FPGA Power Wiki page.
Figure 1: Arria V FPGA Total Power Comparisons by Applications
Figure 2 illustrates a more detailed power comparison showing the total power consumption of an Arria V FPGA alongside the power consumption of 1.0-V and 0.9-V versions of a Kintex-7 FPGA in the same broadcast studio application. As indicated in the comparison, the standard Arria V device consumes the least total power, even compared to the lowest power offerings from competitors.
Figure 2: Total Power of Arria V FPGA Compared to 1.0-V and 0.9-V Competing FPGAs Using a 16-Input, 8-Channel Audio/Visual (A/V) Switcher
Lowest Static Power in the Mid Range
By leveraging the 28LP process and a balanced selection of transistors with low threshold voltage (VT) and high VT, Arria V FPGAs consume the lowest static power of any mid-range FPGA. Under typical or worst-case conditions, Arria V FPGAs consume less than half the static power than Xilinx Kintex-7 FPGAs, as shown in Figure 3.
Figure 3: Arria V FPGA Static Power vs. Competing FPGAs 
Lowest Transceiver Power in the Mid Range
Arria V FPGAs also offer the lowest power serial transceivers available for a mid-range FPGA. At 3.125 Gbps, the transceivers in Arria V FPGAs consume less than 80 mW of total power per channel; at 6.375 Gbps, Arria V transceiver channels consume less than 100 mW of power, and at 10.3125 Gbps, consume less than 130 mW of power, which is one-half to one-third that of competing 28-nm FPGAs, as shown in Figure 4.
Figure 4: Arria V FPGA Transceiver Power per Channel
With up to 36 transceiver channels in Arria V FPGAs, transceiver-rich designs can easily fit within their power budgets by using the industry’s most power-efficient transceivers. Additionally, any unused transceivers can be shut down, giving you the ultimate control over your design’s power consumption.
Furthermore, the new multiport memory controller hard IP block and the PCI Express® (PCIe®) hard IP block reduce power consumption by over 50 percent compared to soft-logic implementations. These blocks, along with the fractional phase-locked loops (fPLLs) in the FPGA, can also be shut down if unused, further lowering your design's total power consumption.
Compared with Altera's previous generation of mid-range FPGAs, Arria V FPGAs offer a 40 percent power reduction on average, with power reduction from all areas, as shown in Figure 5.
Figure 5. Power Consumption: Arria V FPGA vs. Arria II FPGA
Accurate Power Estimation and Analysis
Altera makes power estimation and analysis from design concept through implementation easy with the industry's most accurate and complete power management design tools. Altera offers the following power estimation and analysis resources:
You can use the PowerPlay EPE during the design concept phase and the PowerPlay power analyzer during the design implementation phase. The PowerPlay EPE is a spreadsheet-based analysis tool that enables early power scoping based on device and package selection, operating conditions, and device utilization. The power models in the PowerPlay EPE correlate to silicon, ensuring an accurate estimation of your design's power consumption.
The PowerPlay power analyzer is a far more detailed power analysis tool that uses actual design placement and routing, logic configuration, and simulated waveforms to accurately estimate dynamic power. The power analyzer, in aggregate, provides ±10 percent accuracy when used with accurate design information. Quartus II software PowerPlay power models correlate to silicon measurements based on over 5,000 test configurations per circuit.
Throughout the design process, the Power Management Resource Center provides useful information regarding power, thermal management, and power supply management.
Quartus II Software Power Optimization
Design implementation details can improve performance, minimize area, and reduce power. Historically, the performance and area trade-offs are automated within the register transfer level (RTL) through the
placement-and-routing design flow. Altera has taken a leadership position in bringing power optimization into the design flow. Quartus II software PowerPlay optimization tools automatically use the Arria V FPGA architecture capabilities to further reduce power, resulting in up to 10 percent lower total power consumption when enabled.
Quartus II software has many automatic power optimizations that are transparent to you, but provide optimal utilization of FPGA architecture details to minimize power, including the following:
- Transforming major functional blocks
- Mapping user RAMs so they use less power
- Restructuring logic to reduce dynamic power
- Selecting correct logic inputs to minimize capacitance on high-toggling nets
- Reducing area and wiring demands for core logic to minimize dynamic power in routing
- Modifying placement to reduce clocking power
Related Links
- Meeting the Low Power Imperative at 28nm (PDF) white paper
- Introduction to Arria V FPGAs webcast
- FPGA Power Management and Modeling Techniques (PDF) white paper
- Quartus II software PowerPlay power analysis and optimization technology
- Power Management Resource Center
- Power Optimization (PDF) chapter of the Quartus II Development Software Handbook
