Whether you need two channels of transceivers, or tens, Arria V FPGAs provide the right balance of cost, power, and performance to deliver exactly what you need to succeed. Flexible clocking, superior signal integrity (SI), the lowest power 10G transceivers, and the highest quantity of 6G transceivers are only a handful of the ways the Arria® V FPGAs have been designed for power-sensitive, high-bandwidth applications.
Key Transceiver Features
- Up to 36 transceivers supporting data rates from 0.6 Gbps – 6.375 Gbps on Arria V GX FPGAs
- Up to 6 transceivers supporting data rates from 0.6 Gbps – 10.3125 Gbps on Arria V GT FPGAs
- Linear equalizer to compensate for backplane channel losses
- 3-tap pre-emphasis to minimize intersymbol interference
Optimized for Low Power and Low System Cost
- A single 6.375-Gbps channel will consume 90 mW of power
- A single 10.3125-Gbps channel will consume 135 mW of power
- On-package/die separation of core/transceiver power supplies minimizes board complexity, allowing Arria V systems to be powered by as few as 3 total regulators
Powerful Setup and Debug Tools
- Dynamic reconfiguration to adjust transceiver parameters in a live system
- Pattern generators/checkers to measure bit error rates (BERs) on multiple channels
- AutoSweep to sweep PMA settings and report the ideal configuration
Flexible Clocking
- Each channel can be configured as a data channel or as a clock management unit
- Receive clocking: Analog PLL-based clock data recovery (CDR) per receive channel
- Transmit clocking: Clock management unit or fractional PLL
The figure below shows the blocks that make up the Arria V transceivers.
Figure 1. Arria V Transceivers, PMA, and PCS Block Diagram
