Whether you need a few channels of transceivers, or up to 36, Arria® V FPGAs provides transceiver solutions to meet your performance and power requirements to deliver exactly what you need to succeed. Flexible clocking, superior signal integrity (SI), the lowest power transceivers, and the highest quantity of transceivers are only a handful of the ways the Arria V FPGAs have been designed for power-sensitive, high-bandwidth applications.
Table 1. Comparison of Arria V Variants Transceiver Features
|Features||Arria V GZ||Arria V GT||Arria V GX|
|Maximum number of transceivers||36||36||36|
|12.5 Gbps backplane capable transceivers|
|10.3125 Gbps transceivers for SFF-8431 applications|
|6.375 backplane capable transceivers|
Continuous-time linear equalization - Receiver 4-stage linear equalization
|Decision feedback equalization - Receiver 5-tap digital equalizer|
|Adaptive equalization - Automatically adjust equalization|
|Transmit equalization pre-emphasis (4-Tap)|
|Transmit equalization pre-emphasis (3-Tap)|
|Ring oscillator transmit PLLs|
|LC oscillator PLLs|
|On-die instrumentation (EyeQ data-eye monitor)|
Each Arria V FPGA transceiver consists fo the Phyiscal Media Attachment, Physcial Coding Sublayer, and hardened IP blocks with added clocking flexibilities and more independent channels. Every channel has a full PMA and PCS along with a dedicated independent receive analog PLL CDR. To make it easier for designers to meet transceiver speeds up to 12.5 Gbps, drive up to 40" of backplane, and implement PCIe Gen3, Arria V GZ contains a number of additional features as illustrated in Table 1 and Figure 1.
Figure 1: Arria V GZ FPGA Transceiver Channel Components
*Note: Arria V GX, and GT do not have Adaptive LinearEQ, EyeQ, PCIe Gen3 and select hardened IP that Arria V GZ has.
Otimized for Low Power and Low System Cost
- A single 10.3125-Gbps channel will consume < 165 mW of power
- A single 12.5-Gbps channel will consume < 200 mW of power