Cyclone® V FPGAs continue the Cyclone device family tradition of an unprecedented combination of low power, high functionality, and low cost. The Cyclone V FPGA now includes an optional integrated hard processor system (HPS) – consisting of processors, peripherals, and memory controller – with the FPGA fabric using a high-bandwidth interconnect backbone. The combination of the HPS with Altera's 28 nm low-power FPGA fabric provide the performance and ecosystem of an applications-class ARM® processor with the flexibility, low cost, and low power consumption of the Cyclone V FPGAs.
The Cyclone V FPGA core architecture comprises the following:
- Up to 300K equivalent logic elements (LEs) arranged as vertical columns of adaptive logic modules (ALMs)
- Up to 12 Mb of embedded memory arranged as 10 Kb (M10K) blocks
- Up to 1.7 Mb of distributed memory logic array blocks (MLABs)
- Up to 342 variable-precision digital signal processing (DSP) blocks that can implement up to 684 18x18 embedded multipliers.
- Eight fractional clock synthesis phase-locked loops (PLLs)
All of these logic resources are interconnected through a highly flexible clocking network, with over 30 global clock trees and a power-optimized version of Altera's high-performance MultiTrack routing architecture.
Figure 1. Key Architectural Features of Cyclone V FPGA Series
Flexible Interface Support
Cyclone V FPGAs provide flexible interface support with up to 12 5-Gbps transceivers on the left side of the die. The logic and routing core fabric is surrounded by I/O elements and PLLs, as shown in Figure 1. Cyclone V devices have two to eight PLLs. The I/O elements support 840 MHz LVDS and 800 Mbps of external memory bandwidth. These I/O elements provide support for all mainstream differential and single-ended I/O standards including 3.3 V LVTTL at up to 16-mA drive strength.
Abundant Hard IP
Cyclone V FPGAs include hard intellectual property (IP) blocks, such as an ARM-based HPS, up to two PCI Express® (PCIe®) hard IP blocks, and up to two hardened multiport memory controllers. The hardened PCIe block supports widths up to four lanes for Gen1 and four lanes for Gen2 applications, and now includes multifunction support. Multifunction support allows up to eight peripherals to share a single PCIe link with individual memory map and control and status registers (CSRs) to simplify software driver development. The hardened multiport memory controller can arbitrate between up to six different masters and offers command and data reordering to maximize the efficiency of your DRAM link.
To protect your valuable IP investments, Cyclone V FPGAs also provide the most comprehensive design protection available in FPGAs, including 256 bit Advanced Encryption Standard (AES) bitstream encryption, JTAG port protection, internal oscillator, zeroization (active clear), and cyclic redundancy check (CRC) features.