Cyclone V FPGA Family Overview

Altera's Cyclone^® V FPGAs provide the industry's lowest system cost and power, along with performance levels you need to differentiate your high-volume applications. Choose from the following variants:

Cyclone V E FPGAs with logic only
Cyclone V GX FPGAs with 3.125 Gbps transceivers
Cyclone V GT FPGAs with 6.144 Gbps transceivers
Cyclone V SE SoC FPGA with ARM^®-based hard processor system (HPS) and logic
Cyclone V SX SoC FPGA with ARM-based HPS and 3.125 Gbps transceivers
Cyclone V ST SoC FPGA with ARM-based HPS and 5 Gbps transceivers

Table 1. Cyclone V E FPGA Family Overview

Device	5CEA2	5CEA4	5CEA5	5CEA7	5CEA9
Logic elements (LEs) (K)	25	49	77	149.5	301
M10K memory blocks	176	308	446	686	1,220
M10K memory (Kb)	1,760	3,080	4,460	6,860	12,200
Memory logic array blocks (MLABs) (Kb)	196	303	424	836	1,717
18-bit x 18-bit multipliers	50	132	300	312	684
Variable-precision digital signal processing (DSP) blocks (1)	25	66	150	156	342
Fractional phase-locked loops (PLLs)	4	4	6	7	8
Maximum user I/Os	224	224	240	480	480
Memory controllers	1	1	2	2	2
Availability	Contact Sales	Contact Sales	Contact Sales	Buy Now	Contact Sales

Note:

DSP blocks include three 9x9, two 18x19, and one 27x27 multiplier. Other modes are also available.

Table 2. Cyclone V E Device Packages and Maximum User I/Os (1)

Device/ Package (mm x mm)	M383		M484		F256		U324		U484		F484		F672		F896
	0.5 mm 13 x 13		0.5 mm 15 x 15		1.0 mm 17 x 17		0.8 mm 15 x 15		0.8 mm 19 x 19		1.0 mm 23 x 23		1.0 mm 27 x 27		1.0 mm 31 x 31
	I/Os	XVCRs	I/Os	XVCRs	I/Os	XVCRs	I/Os	XVCRs	I/Os	XVCRs	I/Os	XVCRs	I/Os	XVCRs	I/Os	XVCRs
5CEA2	223²	-	-	-	128	-	176	-	224	-	224	-	-	-	-	-
5CEA4	223²	-	-	-	128	-	176	-	224	-	224	-	-	-	-	-
5CEA5	175	-	-	-	-	-	-	-	224	-	240	-	-	-	-	-
5CEA7	-	-	240	-	-	-	-	-	240	-	240	-	336	-	480	-
5CEA9	-	-	-	-	-	-	-	-	240	-	224	-	336	-	480	-

Note:

Color denotes vertical migration.
175 I/O are migratable to 5CE-A5 M383

Table 3. Cyclone V GX FPGA Family Overview

Device	5CGXC3	5CGXC4	5CGXC5	5CGXC7	5CGXC9
LEs (K)	31.5	50	77	149.5	301
M10K memory blocks	119	250	446	686	1,220
M10K memory (Kb)	1,190	2,500	4,460	6,860	12,200
MLABs (Kb)	159	295	424	836	1,717
18-bit x 18-bit multipliers	102	140	300	312	684
Variable-precision DSP blocks	51	70	150	156	342
PCI Express^® (PCIe^®) hard intellectual property (IP) block	1	2	2	2	2
Fractional PLLs	4	6	6	7	8
Maximum user I/Os	208	336	336	480	560
Memory controllers	1	2	2	2	2
Availability	Contact Sales	Contact Sales	Contact Sales	Buy Now	Contact Sales

Table 4. Cyclone V GX Device Packages and Maximum User I/Os (1)

Device/ Package (mm x mm)	M301		M383		M484		U324		U484		F484		F672		F896		F1152
	0.5 mm 11 x 11		0.5 mm 13 x 13		0.5 mm 15 x 15		0.8 mm 15 x 15		0.8 mm 19 x 19		1.0 mm 23 x 23		1.0 mm 27 x 27		1.0 mm 31 x 31		1.0 mm 35 x 35
	I/Os	XVCRs	I/Os	XVCRs	I/Os	XVCRs	I/Os	XVCRs	I/Os	XVCRs	I/Os	XVCRs	I/Os	XVCRs	I/Os	XVCRs	I/Os	XVCRs
5CGXC3	-	-	-	-	-	-	144	3	208	3	208	3	-	-	-	-	-	-
5CGXC4	129	4	175	6	-	-	-	-	224	6	240	6	336	6	-	-	-	-
5CGXC5	129	4	175	6	-	-	-	-	224	6	240	6	336	6	-	-	-	-
5CGXC7	-	-	-	-	240	3	-	-	240	6	240	6	336	9	480	9	-	-
5CGXC9	-	-	-	-	-	-	-	-	240	5	224	6	336	9	480	12	560	12

Note:

Color denotes vertical migration.

Table 5. Cyclone V GT FPGA Family Overview

Device	5CGTD5	5CGTD7	5CGTD9
LEs (K)	77	149.5	301
M10K memory blocks	446	686	1,220
M10K memory (Kb)	4,460	6,860	12,200
MLABs (Kb)	424	836	1,717
18-bit x 18-bit multipliers	300	312	684
Variable-precision DSP blocks	150	156	342
PCIe hard IP block	2	2	2
Fractional PLLs	6	7	8
Maximum user I/Os	336	480	560
Memory controllers	2	2	2

Table 6. Cyclone V GT Device Packages and Maximum User I/Os (1)

Device/ Package (mm x mm)	M301		M383		M484		U484		F484		F672		F896		F1152
	0.5 mm 11 x 11		0.5 mm 13 x 13		0.5 mm 15 x 15		0.8 mm 19 x 19		1.0 mm 23 x 23		1.0 mm 27 x 27		1.0 mm 31 x 31		1.0 mm 35 x 35
	I/Os	XVCRs	I/Os	XVCRs	I/Os	XVCRs	I/Os	XVCRs	I/Os	XVCRs	I/Os	XVCRs	I/Os	XVCRs	I/Os	XVCRs
5CGTD5	129	4	175	6	-	-	224	6	240	6	336	6	-	-	-	-
5CGTD7	-	-	-	-	240	3	240	6	240	6	336	9	480	9	-	-
5CGTD9	-	-	-	-	-	-	240	5	224	6	336	9	480	12	560	12

Note:

Color denotes vertical migration.

Table 7. Cyclone V SE SoC FPGA Family Overview

Device	5CSEA2	5CSEA4	5CSEA5	5CSEA6
LEs (K)	25	40	85	110
Adaptive logic modules (ALMs)	9,434	15,094	32,075	41,509
M10K memory blocks	140	224	397	514
M10K memory (Kb)	1,400	2,240	3,972	5,140
MLABs (Kb)	138	220	480	621
18-bit x 19-bit multipliers	72	116	174	224
Variable-precision DSP blocks *(1)*	36	58	87	112
FPGA PLLs	4	5	6	6
HPS PLLs	3	3	3	3
Maximum FPGA user I/Os	145	145	288	288
Maximum HPS I/Os	188	188	188	188
FPGA hard memory controllers	1	1	1	1
HPS hard memory controllers	1	1	1	1
Processor cores (ARM Cortex^TM-A9 MPCore^TM)	Single or dual	Single or dual	Single or dual	Single or dual

Note:

DSP blocks include three 9x9, two 18x19, and one 27x27 multiplier. Other modes are also available.

Table 8. Cyclone V SE SoC FPGA Device Packages and Maximum User I/Os

Device/ Package (mm x mm)	U484		U672		F896
	0.8 mm 19 x 19		0.8 mm 23 x 23		1.0 mm 31 x 31
	FPGA I/Os	HPS I/Os	FPGA I/Os	HPS I/Os	FPGA I/Os	HPS I/Os
5CSEA2	66	161	145	188	-	-
5CSEA4	66	161	145	188	-	-
5CSEA5	66	161	145	188	288	188
5CSEA6	66	161	145	188	288	188

Table 9. Cyclone V SX SoC FPGA Family Overview

Device	5CSXC2	5CSXC4	5CSXC5	5CSXC6
LEs (K)	25	40	85	110
ALMs	9,434	15,094	32,075	41,509
M10K memory blocks	140	224	397	514
M10K memory (Kb)	1,400	2,240	3,972	5,140
MLABs (Kb)	138	220	480	621
18-bit x 19-bit multipliers	72	116	174	224
Variable-precision DSP blocks	36	58	87	112
Maximum transceivers	6	6	9	9
PCIe hard IP block	2	2	2	2
FPGA PLLs	4	5	6	6
HPS PLLs	3	3	3	3
Maximum FPGA user I/Os	145	145	288	288
Maximum HPS I/Os	188	188	188	188
FPGA hard memory controllers	1	1	1	1
HPS hard memory controllers	1	1	1	1
Processor cores (ARM Cortex-A9 MPCore)	Dual	Dual	Dual	Dual

Table 10. Cyclone V SX SoC FPGA Device Packages and Maximum User I/Os

Device/Package (mm x mm)	U672			F896
	0.8 mm 23 x 23			1.0 mm 31 x 31
	FPGA I/Os	HPS I/Os	XCVRs	FPGA I/Os	HPS I/Os	XCVRs
5CSXC2	145	188	6	-	-	-
5CSXC4	145	188	6	-	-	-
5CSXC5	145	188	6	288	188	9
5CSXC6	145	188	6	288	188	9

Table 11. Cyclone V ST SoC FPGA Family Overview

Device	5CSTD5	5CSTD6
LEs (K)	85	110
ALMs	32,075	41,509
M10K memory blocks	397	514
M10K memory (Kb)	3,972	5,140
MLAB (Kb)	480	621
18-bit x 19-bit multipliers	174	224
Variable-precision DSP blocks	87	112
Maximum transceivers	9	9
PCIe hard IP block	2	2
FPGA PLLs	6	6
HPS PLLs	3	3
Maximum FPGA user I/Os	288	288
Maximum HPS I/Os	188	188
FPGA hard memory controllers	1	1
HPS hard memory controllers	1	1
Processor cores (ARM Cortex-A9 MPCore)	Dual	Dual

Table 12. Cyclone V ST SoC FPGA Device Packages and Maximum User I/Os

Device/Package (mm x mm)	F896
	1.0 mm 31 x 31
	FPGA I/Os	HPS I/Os	XCVRs
5CSTD5	288	188	9
5CSTD6	288	188	9

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Cyclone V FPGA Family Overview

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