Cyclone V FPGA Multiport Memory Controller

The multiport memory controller hard intellectual property (IP) block brings a new level of productivity and time-to-market advantage. The advanced features for supporting command and data reordering significantly increases the efficiency of your DRAM interface. The multiport memory controller eases timing closure and reduces I/O count by allowing up to six functions to share a single memory device, therefore saving PCB space and increasing bus efficiency. As a result, you save time, system cost, and power.

The multiport memory controller IP supports the following features:

• User configurable timing parameters set during compilation or during FPGA operation
• Support for up to 4 GB external memory devices
• Two chip selects
• Configurable memory width of 8, 16, 24, 32, and 40 bits
• Hard error correction code (ECC) support for 16-bit and 32 bit data widths
• Flexible fabric interface port configuration with up to six command ports and up to 256 bits of data
• Bonding of two controllers to service higher bandwidth applications by creating a virtual x64 memory
• DRAM power savings, including auto-refresh and deep power down

The multiport memory controller consists of two major blocks as shown in Figure 1:

• Multiport front end—handles the arbitration of memory reads and writes between up to six masters
• PHY—interfaces between the memory controller and the memory devices. Performs the actual read and write operations to and from the external memory.

Figure 1: Multiport Memory Controller Architecture

The multiport front end provides the following arbitration and reordering features:

• Command and data reordering to boost bus efficiency
• Out-of-order execution of DRAM commands
• Collision detection and in-order return of results
• Dynamically configurable priority support with both absolute and relative priority scheduling

The PHY interface on the multiport memory controller offers the following calibration features for data sequencing and timing control:

• Hardened read FIFO buffer in input register path
• Dedicated DDR registers in the I/O elements
• Dynamic deskew delays with 25 ps resolution to optimize the sampling window
• Skew adjustment circuitry to allow full path calibration from FPGA logic to the memory device on both read and write paths
• On-chip termination calibration to limit termination impedance variation
• On-chip dynamic termination to swap between serial and parallel termination for optimal signal integrity
• DLL delay chain for temperature-compensated DQS phase shifts

The multiport memory controller hard IP in the Cyclone^® V FPGA supports DDR3 SDRAM, DDR2 SDRAM, and LPDDR2 (single-rank support only). The Cyclone V FPGA also supports the soft memory controllers for the memory interfaces mentioned. For a complete list of memory interface support and performance, see Table 1.

Table 1. Memory Interface Performance on Cyclone V FPGAs