Not all low-cost transceivers are created equally. Altera's Cyclone® V FPGA family has a flexibility that helps you fully utilize all available transceiver resources and keep designs in a smaller and lower cost device. The Cyclone V FPGAs provide the most flexibility in implementing independent protocols, implementing proprietary protocols with hardened building block, all at the lowest power possible.
By providing the market's lowest cost, lowest power FPGAs, Altera's Cyclone V FPGA family extends the Cyclone FPGA series. Altera's transceiver leadership is re-affirmed with actual shipment of working transceiver I/O within an FPGA design. Watch the video below to see Cyclone V FPGAs in action.
Cyclone V FPGA Video: Transceiver I/O Operation
The Cyclone V FPGA series offers two variants to meet your design needs, the Cyclone V GX FPGAs with transceivers up to 3.125 G and Cyclone V GT FPGAs with transceivers up to 6.144 G.
Key Transceiver Features
- Up to twelve transceivers supporting data rates from 600 Mbps to 3.125 Gbps or 6.144 Gbps
- Flexible and easy-to-configure transceiver datapath to implement industry-standard and proprietary protocols
- Programmable pre-emphasis settings and adjustable differential output voltage (VOD) for improved signal integrity (SI)
- User-controlled receiver equalization to compensate for frequency-dependent losses in the physical medium
- Dynamic reconfiguration of the transceiver to support multiple protocols and data rates on the same channel without reprogramming the FPGA
- Support for protocol features such as spread-spectrum clocking in PCI Express® (PCIe®), Common Public Radio Interface (CPRI), DisplayPort, V-by-One, and SATA configurations
- Dedicated circuitry compliant with the physical interface for PCIe, XAUI, and Gbps Ethernet (GbE)
- PIPE interface that connects directly to embedded PCIe Gen1 (2.5 Gbps) and Gen2 (5 Gbps) hard intellectual property (IP) to support PCI-SIG® compliant x1, x2, or x4 endpoint or rootport applications
- Built-in byte ordering so that a frame or packet always starts in a known byte lane
- 8B/10B encoder and decoder that performs 8 bit to 10 bit encoding and 10 bit to 8 bit decoding
- On-die power supply regulators for transmitter and receiver phase-locked loop (PLL) charge pump and voltage controlled oscillator (VCO) for superior noise immunity
- On-chip power supply decoupling to satisfy transient current requirements at higher frequencies, which reduces the need for on-board decoupling capacitors
- Diagnostic features such as serial loopback, parallel loopback, reverse serial loopback, and loopback master and slave capability in the PCI-SIG compliant PCIe hard IP block
Figure 1 shows the block diagram of the Cyclone V FPGA transceivers, both physical medium attachment (PMA) and physical coding sublayer (PCS). The blocks within the PCS can be bypassed, depending on your requirements.
Figure 1. Cyclone V FPGA Transceivers, PMA, and PCS Block Diagram