Cyclone™ devices have up to two enhanced phase-locked loops (PLLs) that provide advanced clock management capabilities such as frequency synthesis, programmable phase shift, external clock output, programmable duty cycle, lock detection, and high-speed differential support on the input and output clocks. The PLLs in Cyclone devices simplify timing issues and overall board layout. Cyclone PLLs provide cost-efficient timing control for applications, including consumer, communications, computing, automotive, industrial and wireless systems. Figure 1 shows a block diagram of the Cyclone PLLs.Figure 1. Cyclone Device PLL Block Diagram
Clock Multiplication & Division
Cyclone PLLs provide a clock synthesis capability that allows the internal clocks to operate at a different frequency than the input clock frequency. Each PLL can provide up to three clock outputs that can operate at different frequencies. The PLLs offer a frequency multiplication by m or division by (n x post-scale counter) scaling factor, where m, n, and the post-scale counter can be any integer from 1 to 32.
Cyclone PLLs allows designers to implement time-domain multiplexed applications where a given circuit is used more than once per clock cycle. By using time-domain multiplexing, you can implement a given function with fewer logic cells thereby improving device area efficiency by sharing resources within the device.
External Clock Outputs & Clock Feedback
Each PLL supports one differential or one single-ended external output clock. There is one external clock output pin pair per PLL. The external clock output pins support various I/O standards as shown in Table 1. The external clock output can be used for system clocking or for synchronizing different devices on the board. The clock feedback feature can compensate for internal delay or can phase-align the external clock output with the clock input.
|Table 1. Cyclone PLL Features|
|Clock Multiplication & Division||m/(n x post-scale counter) (1)|
|Phase Shift||Resolution up to 150-ps increments (2), (3)|
|Programmable Duty Cycle||3|
|Number of Internal Clock Outputs||2|
|Number of External Clock Outputs||Up to one differential or one single-ended|
|I/O Standard Support on Input Clock & External Clock Output||LVTTL, LVCMOS, 2.5/1.8/1.5 V, 3.3-V PCI, SSTL-2 Class I & II, SSTL-3 Class I & II, LVDS|
Notes to Table 1:
- The m counter, n counter, and the post-scale counters range from 1 to 32.
- The smallest phase shift is determined by the VCO period divided by 8.
- For degree increments, Cyclone devices can shift all output frequencies in increments of at least 45°. Smaller degree increments are possible depending on the frequency and divide parameters.
Programmable Phase Shift
Cyclone PLLs have advanced clock shift capability to enable programmable phase shifts. Designers can perform phase shifting in time units with a resolution of up to 150 picoseconds. The programmable phase shift feature is ideal for meeting timing constraints such as set-up and hold times where the exact location of the clock edge is critical.
Lock Detect Signal
The lock output indicates that there is a stable clock output signal in phase with the reference clock. The lock detect signal can be used for system control and synchronization of different devices on the board.
Programmable Duty Cycle
The programmable duty cycle allows PLLs to generate clock outputs with a variable duty cycle. The programmable duty cycle feature is useful in double data rate (DDR) applications where the data is transferred on both the positive and the negative edge of the clock. Programmable duty cycle allows the designer to manipulate the position of the positive and negative edges of the clock, which simplifies set-up and hold time requirements associated with these edges.