Cyclone III FPGA: Architecture

Cyclone^® III FPGAs offer an unprecedented combination of low power, high functionality, and low cost. The architecture consists of up to 120K vertically arranged logic elements (LEs), 4 Mbits of embedded memory arranged as 9-Kbit (M9K) blocks, and 200 18x18 embedded multipliers. Cyclone III LS FPGAs have a memory-rich and multiplier-rich floorplan consisting of up to 200K logic elements, 8.2 Mbits of embedded memory, and 396 embedded multipliers.

Both architectures include highly efficient interconnect and low-skew clock networks, providing connectivity between logic structures for clock and data signals. The logic and routing core fabric is surrounded by I/O elements (IOEs) and phase-locked loops (PLLs), as shown in Figure 1.

Figure 1. Cyclone III FPGA Floorplan

Figure 1. Cyclone III Floorplan

Key Features	Connectivity
Power Density Embedded 18 x 18 Multipliers Embedded Memory Cost-Optimized Architecture Clock Management	External Memory Interfaces I/O Flexibility Interface and Protocol Support Signal Integrity On-Chip Termination
Market Specific Features
Remote System Upgrades SEU Mitigation

Cyclone III FPGA: Architecture

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