Building on the success of 130-nm Cyclone® and 90-nm Cyclone II device families, Altera introduces the 65-nm Cyclone III family of FPGAs, the lowest-cost FPGAs ever. Cyclone III FPGAs enable the development of new, programmable solutions in high-volume, cost-sensitive applications where FPGAs were once considered too expensive.
Challenges of Cost Optimization
When designing low-cost FPGAs, you need to address the tradeoff between power, performance, features, and overall device cost. You are challenged to go to market in a hurry with premium quality, cutting-edge products that can be offered at reasonable a price (Figure 1).
Figure 1. Balancing Power, Performance, Features & Cost
Getting Much More for Much Less
Altera helps you turn your ideas into revenue faster with a cost-optimized FPGA architecture that provides optimal performance for Cyclone III FPGAs in target applications such as wireless, video and image processing, and display.
Altera adopted a new design methodology to ensure Cyclone III FPGAs would successfully meet low-cost goals for high-volume applications. The traditional "optimization-by-elimination" approach involves reducing the cost of an existing high-density product by eliminating features in software. Although this method is marginally effective in reducing FPGA cost, it does not attain the lowest possible price points for a given die size and package.
In contrast, the design methodology used by Altera to build the Cyclone III device family did not rely on the re-purposing of existing products. Similar to the process used for the previous Cyclone and Cyclone II family architectures, the Cyclone III architecture definition was inspired by customers like you who help to define key low-cost features and application advantages from the start.
Altera's ability to move Cyclone III FPGAs into high volume fast also contributes to the device family’s low cost. Altera’s strategy of being first to volume on new product announcements gives you the highest quality products when you want them, and in the quantity you need.
Early in the life of each new process, foundry partner TSMC collaborates with Altera in multiple areas to solve all critical issues, including design for manufacturability (DFM) and performance optimization. Together, design and process teams overcome the technological challenges of each process node to ensure success, and to see that Altera continues to lead the industry in volume production.
Cyclone III FPGAs take advantage of the benefits of 65-nm technology (small die size, high density and low cost) with up to three speed grades higher performance than competing low-cost FPGAs.
Cyclone III FPGAs are pad limited. A pad-limited die means the I/O structure is as small as possible, and therefore the die cost is at its lowest. In addition, the Cyclone III FPGAs offer staggered I/O pads, meaning that two rows of I/O pads are interleaved, increasing the number of available I/O pads.
Cyclone III FPGAs were built starting with the careful selection of small form-factor packages that offer sufficient user I/O pins and the lowest-cost structure. From the physical dimensions of the package, the maximum size of a pad-limited die can be determined. The logic is then populated with as many logic elements (LEs), memory blocks, dedicated multipliers, and other customer-defined features as possible, guaranteeing the most functionality in the available area.
