Leading-edge ASIC designs are becoming more expensive and time-consuming because of the increasing cost of mask sets and the amount of engineering verification required. Getting a device right the first time is imperative. A single missed deadline can mean the difference between profitability and failure in the product life cycle. Figure 1 shows how the impact that time-to-market delays can have on product sales.
Using an FPGA to prototype an ASIC or ASSP for verification of both register transfer level (RTL) and initial software development has now become standard practice to both decrease development time and reduce the risk of first silicon failure. An FPGA prototype accelerates verification by allowing testing of a design on silicon from day one, months in advance of final silicon becoming available. Code can be compiled for the FPGA, downloaded, and debugged in hardware during both the design and verification phases using a variety of techniques and readily available solutions. Whether you're doing RTL validation, initial software development, or system-level testing, FPGA prototyping platforms provide a faster, smoother path to delivering an end working product.
Altera's Stratix® series of FPGAs is ideal for ASIC prototyping, offering the highest density of any FPGA available today. Designs of up to 11+ million ASIC gates (i.e., 2-input NAND gates), 52 megabits (Mb) of memory, and 704 digital signal processing (DSP) blocks, available as additional resources, can be implemented in a single Stratix V FPGA. See Table 1 for details of the larger devices in the Stratix IV and Stratix V FPGA families.
|Table 1. Largest Devices of Stratix IV and Stratix V FPGA Families|
|Device||Logic Elements (LEs)||ASIC Gates||User I/Os||Total
|18 x 18
|Phase-Locked Loops (PLLs)|
For larger ASIC designs that don't fit into a single FPGA, using multiple FPGAs for prototyping becomes a matter of partitioning a design across FPGAs and ensuring that design interconnects (e.g. bus signals) are maintained. Using the biggest FPGA available reduces the number of FPGAs required to implement a prototype, reducing the number of interconnects required between devices. For any interconnect scheme, Stratix series FPGAs offer the highest performance with best-in-class signal integrity I/O pins, whether using LVDS or SSTL. This allows the FPGA prototype to perform as close to the initial design goals of the ASIC as possible.
Our largest Stratix series FPGAs are fully supported by major ASIC EDA vendors for software solutions, as well as third-party board vendors for off-the-shelf multi-FPGA solutions. Altera's Quartus® II development software integrates into design flows that are close to, if not identical to, a typical ASIC flow, reducing the amount of learning required when using a new software tool. In addition, the tools can be invoked using scripting to match commonly used ASIC design methodologies.
Our largest Stratix series FPGAs also offer the industry's only low-risk development path from FPGA prototype to high-volume ASIC production with support for migration to HardCopy® ASICs. Designing for a HardCopy series ASIC allows you to reduce development costs and still get the flexibility and time-to-market advantages associated with an FPGA.
All of the Altera® intellectual property (IP) cores that support Stratix series FPGAs can be licensed for use in an ASIC. The advantage of an Altera IP core is that the IP is optimized to the Stratix family architecture, allowing it to run at ASIC-like speeds.
ASIC Prototyping EDA Partners
To aid and support the development of high-density designs, Altera has developed an ecosystem of EDA software partners and development board partners that help facilitate the complete design process.
ASIC Prototyping Third-Party Board Partners
Altera third-party board partners provide off-the-shelf ASIC prototyping and verification solutions utilizing Altera FPGAs.