The Stratix® family of FPGAs introduced the concept of TriMatrix memory. In TriMatrix memory, the on-chip memory is implemented in three types of different block sizes, each for a specific use. The memory type has been maintained and optimized through devices in the Stratix series.
With significant architectural changes to the internal memory in Stratix V FPGAs, we've significantly increased both the capacity and bandwidth of these structures. Stratix V FPGAs utilize two types of memory: enhanced memory logic array blocks (MLABs) and M20K memory blocks. These changes have enhanced performance and utilization, improving capabilities for digital signal processing (DSP) designs. Quartus® II software automatically migrates designs from previous Stratix series FPGA memory architectures to the new structure.
Key enhanced MLAB features improve efficiency and bandwidth:
- Address and data registers internal to MLAB
- Increased performance
- Reduced logic use
- Increased efficiency for wide, shallow FIFOs (n bits wide, 32 or 64 deep)
Key M20K memory block features enhance performance and utilization:
- Increased embedded memory bit counts
- Increased memory block performance
- Improved flexibility of memory architecture to span applications
- Simplified floorplanning and routability
- Optional hard error correction code (ECC) protection, which can operate in pipelined or non-pipelined modes
Quartus II software selects the best-fit memory for each instantiation to provide the most efficient embedded memory implementation.
Table 1 summarizes the differences in the memory blocks and related applications between recent Stratix FPGA families.
| Table 1. Comparison Between TriMatrix Blocks in Stratix III, Stratix IV, and Stratix V FPGAs | ||
| Memory Functions | Stratix III/IV | Stratix V |
|---|---|---|
|
M144K 144K bits |
M20K 20K bits |
|
M9K 9K bits |
|
|
MLAB 640 bits |
Enhanced MLAB 640 bits |
For full details on memory block capacity for Stratix V devices, see the Stratix V overview page.
For details on the memory block counts for earlier Stratix FPGA families, see the relevant handbook chapters.
Table 2 summarizes the features for each of the two internal memory types implemented in Stratix V FPGAs.
| Table 2. Internal Memory Features in Stratix V FPGAs | ||
| Feature | MLAB | M20K |
|---|---|---|
| Performance | 600 MHz | 600 MHz |
| Simple Dual-Port |  |
|
| True Dual-Port | - | |
| Parity | |
|
| Packed Mode | - | |
| ECC | |
|
| Low-Power Mode | |
|
| Shift Register | |
|
| FIFO | |
|
| Initialization | |
|
| Mixed Clock | |
|
| Byte Enable | |
|
| Address Clock Enable | |
|
