Altera's Stratix II GX FPGA Optimized Protocol Solutions

Standard serial protocols are now commonly used for both chip-to-chip, backplane, and cable- or line-side applications. Altera's fully verified protocol solutions are easy to implement and can be quickly embedded into systems with full confidence they will operate to the required standard. This allows you to then concentrate on the core functionality of your design.

Altera provides complete solutions to aid you in using standard protocols for high-speed serial I/O. The solutions, which are based on Stratix^® II GX devices, combine the key building blocks for protocol implementation including:

• Functional intellectual property (IP) blocks
• Protocol-specific development kits
• Reference designs
• Compliance testing
• Interoperability testing
• Characterization and system validation reports
• Quartus^® II development tool support
• Signal integrity modeling (IBIS, SPICE, DML)
• Support collateral

The solutions have been developed in collaboration with experienced design engineers to simplify implementation, improve productivity and mitigate risk.

Table 1 provides an overview of the Altera^® Stratix II GX FPGA complete protocol solutions.

Architecture and IP

The Stratix II GX architecture is aligned for protocol support and provides the building blocks needed to sustain the key functions of the physical layer of the protocol. This reduces the amount of FPGA logic needed for core functions and retains the performance of the data path while simplifying implementation.

The transceiver is capable of supporting a data rate between 600 Mbps and 6.375 Gbps, ensuring the device supports today's data rates as well as having a level of rate growth available within the end design for future protocols as they evolve.

• Stratix II GX Transceiver FPGAs Overview
• Stratix II GX Physical Coding Sub-Layer

Upper levels of the protocol are serviced by flexible intellectual property cores, pre-tested, and verified by Altera Megafunction Partners Program (AMPP^SM) partners. The cores are aligned to match the key functions of the transceiver—to further simplify implementation.

Development Platforms

Altera provides a number of platforms for protocol development, allowing you to generate your system on real hardware and verify operation. The platforms are supported by a number of reference designs that show operations between different protocol and standard memory interfaces, making them useful for both design examples and for system validation. The platforms are also supported by schematics, board layout files, and guidelines, all of which simplify system design and board layout.

• PCI Express Development Kit, Stratix II GX Edition
• Audio Video Development Kit, Stratix II GX Edition
• Transceiver Signal Integrity Development Kit, Stratix II GX Edition

Characterization

The Stratix II GX transceivers have been fully characterized to show compliance with key protocols. This both proves operation within standards and provides a proof of operation that can then be used as part of the end product's compliance. In addition, Altera conducts testing of Stratix II GX FPGAs with key standard products to ensure the devices will interoperate successfully.

• Stratix II GX Characterization Results
• Stratix II GX Eye Diagram Viewer Online Characterization Tool

Please contact your local Altera sales representative for detailed protocol characterization.

Related Links

High-Speed Serial Solutions

• PCI Express
• Serial RapidIO
• 10-Gigabit Ethernet XAUI
• Gigabit Ethernet
• SDH/SONET Scrambled Backplane
• SDI
• Basic Mode
• SerialLite II

Stratix II GX FPGAs

• Stratix GX II Transceiver Overview