The Industry's Fastest and Highest-Density FPGAs with Transceivers
Stratix® II GX FPGAs meet the demands of today’s high data-bandwidth system requirements, providing specific features to simplify support for many of the high-speed protocols now relying on serial transceivers for physical interfacing.
Altera's Stratix II GX devices combine the industry's fastest and highest-density Stratix II FPGA fabric with up to twenty 600 Mbps to 6.375 Gbps transceivers. These transceivers are optimized to provide excellent jitter performance across the entire data range. The power-optimized transceivers have multiple levels of dynamically controlled pre-emphasis and equalization, helping to provide excellent signal integrity characteristics on a standard FR-4 printed circuit board (PCB) fabric at the highest data rates.
Table 1 highlights several Stratix II GX device features.
| Table 1. Stratix II GX Device Features at a Glance | |
| Feature | Description |
|---|---|
| Transceiver Technology | |
| Plug & Play Signal Integrity | Stratix II GX FPGAs are the first to provide automatic receiver equalization, allowing continuous monitoring and adjustment of equalization settings for channel characteristics, card slot position, manufacturing tolerance, silicon process, voltage, and temperature, variations. |
| Dynamic Reconfiguration | Altera is the first company to offer transceiver dynamic reconfiguration to support multiple protocols, data rates and physical medium attachment (PMA) settings. |
| Transceiver Technical Details | Stratix II GX FPGAs provide up to 20 full-duplex channels operating between 600 Mbps and 6.375 Gbps natively and down to 270 Mbps using over-sampling techniques. Stratix II GX devices are optimized to provide excellent signal integrity, reducing board layout risks. |
| Power-Optimized Transceiver Architecture | Stratix II GX FPGAs are specifically architected to provide a low-power transceiver solution. The transceiver dissipates 250 mW per channel at 6.375 Gbps and only 140 mW per channel at 3.125 Gbps. This is less than half the power of the nearest competing transceiver-based FPGA. |
| Transceiver Physical Medium Attachment (PMA) Details | The Stratix II GX PMA layer includes specific features to improve signal integrity. These include dynamically controllable pre-emphasis, equalization, and configurable differential output voltage (VOD). The transceivers also offer a number of different termination schemes. All these features help to reduce high-speed PCB layout risks. |
| Transceiver Physical Coding Sublayer (PCS) Details | The Stratix II GX PCS provides many of the digital building blocks to support industry-standard protocols. These enable compliance to key protocols including PCI Express® (PCIe®), Gigabit Ethernet (GbE), and XAUI, which when combined with tools, intellectual property (IP), and reference material, deliver a complete solution-to-protocol implementation. |
| SerialLite II | The SerialLite II protocol was designed as a lightweight, point-to-point protocol aimed at providing a small footprint, low latency, and low overhead. Designers using SerialLite II in Stratix II GX devices have a low-risk path for implementing serial I/O standards in their applications. |
| Transceiver Protocols | Stratix II GX FPGA transceivers provide hard IP to support the PCS of a number of protocols, including PCIe, Common Electrical Interface 6 Gbps Long Reach and Short Reach (CEI-6G-LR/SR), serial digital interface (SDI), XAUI, SONET, Serial RapidIOTM standard, GbE, and SerialLite II. |
| Complete Protocol Solutions | Stratix II GX FPGAs are part of Altera's complete solutions for key protocols. The solutions provide device functionality along with IP, collateral, and characterization to simplify protocol implementation. |
| Optimized Board Layout Solution | Stratix II GX FPGA architecture includes a number of signal integrity features and optimized power circuitry to aid PCB designers. The product is supported by development kits, tools, and collateral to reduce the risk for the board designer, reduce the time taken to complete board layout, and reduce the overall system cost and power budget. |
| Source-Synchronous Signaling, High I/O Bandwidth & High-Speed Interfaces | |
| Source-Synchronous Signaling I/O Standards in Stratix II GX Devices | Stratix II GX devices support source-synchronous signaling for data transfer rates as high as 1 Gbps. |
| Stratix II GX Dynamic Phase Alignment (DPA) | Stratix II GX devices feature embedded DPA circuitry. The circuitry simplifies PCB layout by eliminating signal alignment issues that arise from the skew-inducing effects of transmitting signals using source-synchronous signaling techniques over long distances. |
| Differential I/O Support | Stratix II GX FPGAs offer high-speed differential I/O support for data rates up to 1 Gbps and address the high-performance needs of emerging I/O interfaces, including support for the LVDS, LVPECL, and HyperTransport™ standards. |
| Single-Ended I/O Standards in Stratix II GX Devices | Stratix II GX devices support high-bandwidth, single-ended I/O interface standards (SSTL, HSTL, PCITM, and PCI-XTM) needed for today’s demanding system requirements. |
| Source-Synchronous Protocols | Stratix II GX devices support a wide array of high-speed interface standards (SPI-4.2, SFI-4, 10-Gigabit Ethernet XSBI, HyperTransport standard, RapidIO standard, and UTOPIA IV) for flexibility and fast time to market. |
| Signal Integrity | The Stratix II GX standard I/O provides two times better signal integrity performance than Virtex-4, demonstrated with IBIS simulations and pin capacitance measurements. |
| Architecture Performance and Efficiency | |
| Fastest 90-nm FPGA Performance | Built on 90 nm technology, Stratix II GX FPGAs offer unparalleled density and logic efficiency. The new logic structure combined with innovative features such as digital signal processing (DSP) blocks and TriMatrix memory, and robust design software tools allow Altera to offer the industry’s fastest FPGAs ever. |
| Up to 132,540 equivalent LEs & up to 6.7 Mbits of Embedded Memory | With up to 130K equivalent logic elements (LEs) and 6.7 Mbits of embedded RAM, Altera’s Stratix II GX FPGAs deliver a balanced ratio of logic and transceivers to support next-generation system requirements. The innovative logic architecture with adaptive logic modules (ALMs), achieves on average 50 percent faster performance with 25 percent reduced logic utilization compared to previous product families. |
| High-Performance Architecture | In addition to having a revolutionary logic architecture, the high-performance Stratix II GX device architecture consists of a speed-optimized interconnect and a highly efficient clock network that provides connectivity between ALMs, TriMatrix memory blocks, DSP blocks, phase-locked loops (PLLs), and I/O elements (IOEs) to maximize system performance. |
| Density & Logic Efficiency | High density and embedded memory complement the bandwidth and performance of the Stratix II GX device architecture. Stratix II GX high-density devices are ideal for ASIC prototyping, where design verification prior to ASIC tape-out is vital. |
| Differences Between Stratix II GX & Stratix II Devices | Stratix II GX devices are based on the industry's largest and fastest FPGA architecture. They each integrate up to 20 high-speed transceivers capable of operating between 600 Mbps and 6.375 Gbps. The transceivers provide a number of key features to reduce PCB risk and simplify support of industry-standard protocols. |
| Differences Between Stratix II GX & Stratix GX Transceivers | Stratix GX device transceivers deliver best-in-class signal integrity performance with exceptional jitter performance. The Stratix II GX device builds on this to support higher data rates and provide enhanced support of industry-standard protocols, including PCIe, CEI-6G-LR/SR, SDI, XAUI, Serial RapidIO standard, GbE, SONET, and SerialLite II. |
| Design Security | |
| Design Security in Stratix II GX Devices | Stratix II GX devices support design security with configuration bit stream encryption using the 128 bit Advanced Encryption Standard (AES) algorithm. |
| High Memory Bandwidth & High-Speed External Memory Device Interfaces | |
| TriMatrix Memory in Stratix II GX Devices | TriMatrix memory in Stratix II GX FPGAs offers up to 6.7 Mbits of RAM. This advanced memory structure includes three sizes of embedded RAM blocks—M512, M4K, and M-RAM blocks—that can be configured to support a wide range of features. |
| External Memory Interfaces in Stratix II GX Devices | Stratix II GX devices provide advanced external memory interfaces, allowing you to integrate external high-density SRAM and DRAM devices into complex system designs without degrading data-access performance. |
| High-Performance DSP | |
| Stratix II GX DSP Blocks | Stratix II GX devices include high-performance embedded DSP blocks, capable of running at 370 MHz and optimized for DSP applications. The DSP blocks eliminate performance bottlenecks in computationally intensive applications, provide predictable and reliable performance, and result in resource savings without compromising performance. |
| DSP Performance in Stratix II GX Devices | Stratix II GX devices offer higher data processing capacity than DSP processors for maximum system performance. |
| Soft Multipliers in Stratix II GX Devices | Stratix II GX devices provide a flexible implementation of soft multipliers that can be configured for different data width and latency. The soft multipliers provide very high DSP throughput in addition to the DSP blocks. |
| System Clock Management | |
| Stratix II GX Clock Management Circuitry | Each Stratix II GX device has up to 16 high-performance, low-skew global clocks that can be used for clocking high-performance functions or global control signals. Additionally, eight localized (regional) clocks per region increase the total number of clocks for any region to 24. This web of high-speed clock networks, which are tightly coupled with the abundant PLLs, ensures that the most complex design can run at optimal performance and with minimum clocking skew. |
| Stratix II GX Clock Management Features | Stratix II GX devices feature up to 8 programmable PLLs, providing robust clock management and frequency synthesis capabilities for maximum system performance. The PLLs provide high-end features, including clock switchover, PLL reconfiguration, spread-spectrum clocking, frequency synthesis, programmable phase shift, programmable delay shift, external feedback, and programmable bandwidth. These features allow designers to manage system timing on and off the Stratix II GX device. |
| On-Chip Termination | |
| On-Chip Termination in Stratix II GX Devices | Stratix II GX devices feature series and differential on-chip termination that can simplify board layout by minimizing the number of external resistors needed on the PCB. |
| Remote System Upgrade Capabilities | |
| Remote System Upgrades With Stratix II GX FPGAs | Stratix II GX devices feature remote system upgrade capabilities, allowing error-free deployment of system upgrades securely and reliably from a remote location. |
| Automatic Cyclic Redundancy Checking (CRC) | |
| Cyclic Redundancy Check (CRC) | Stratix II GX devices feature automatic 32 bit CRC. A single click in Quartus® II design software simplifies setup and activates the device's built-in CRC. It is the most cost-effective FPGA solution available for single event upset (SEU). |
| Embedded Soft Core Processor | |
| Stratix II GX Devices & Nios II Processors | The advanced architectural features of Stratix II GX devices combined with the Nios® II family of embedded processors offer unparalleled processing power to meet the needs of network, telecommunications, DSP applications, mass storage, and other high-bandwidth systems. Stratix II GX devices improve overall system performance of the latest Nios II processors. |
