All Stratix® II GX device family members are in production.
Stratix II GX combines the industries fastest and largest 90-nm FPGA with up to 20 robust transceivers offering excellent jitter performance with features to optimize signal integrity. This has enabled Stratix II GX devices to offer compliant solutions for the most stringent protocols such as PCI Express, SDH/SONET (STM-4 / OC-12 and STM-16 /OC48), and CEI-6G-LR.
The first stage of the plan included the development of a series of transceiver test chips, which were used by Altera's engineering teams to:
- Correlate performance against models to ensure reliability
- Confirm operation of high-performance features
- Qualify process prior to releasing devices, to improve yield
- Dramatically elevate probability of first-time success with the Stratix II GX FPGA rollout
The transceiver design validated with the test chips was then integrated with the Stratix II FPGA architecture to form the final product. Altera used the same strategy during the successful rollout of Stratix GX devices.
Figure 1 shows an eye diagram from the Stratix II GX device at 6.375 Gbps using an internally generated PRBS10 test pattern at a VOD of 800 mV.
Figure 1. 6.375-Gbps Eye Diagram Taken From Stratix II GX Device
Table 1 shows the rollout plan for the EP2SGX90 device. The device was widely sampled at the end of April 2006. Please bookmark this page to review rollout progress, as it will be continually updated to show the latest status.
| Table 1. EP2SGX90 Device Rollout Plan | ||
| Deliverable | Schedule | Status |
|---|---|---|
| Stratix II Production | December 2004 |  |
| Quartus® II Software Tool Support | October 2005 | |
| Transceiver Test Chip Back | November 2005 | |
| Stratix II GX (EP2SGX90) Tape Out | December 2005 | |
| TC2 Characterization Complete | February 2006 | |
| Stratix II GX (EP2SGX90) Back at Factory | February 2006 | |
| Stratix II GX (EP2SGX90) Released to Lead Customers | March 2006 | |
| Stratix II GX (EP2SGX90) General Sample Availability | April 2006 | |
| Stratix II GX (EP2SGX90) Interim Characterization Report | July 2006 | |
| Stratix II GX in Production | November 2006 | |
Table 2 shows Stratix II GX device features and includes general sampling and production silicon dates.
| Table 2. Stratix II GX Device Features | |||||||
| Device | Transceiver Channels | Equivalent Logic Elements | Total Memory Bits | 18-Bitx18-Bit Multipliers (1) | PLLs (2) | Availability (3) | |
|---|---|---|---|---|---|---|---|
| General Engineering Samples | Production Devices | ||||||
| EP2SGX30C | 4 | 33,880 | 1,369,728 | 64 | 4 | - | Now |
| EP2SGX60C | 4 | 60,440 | 2,544,192 | 144 | 4 | - | Now |
| EP2SGX30D | 8 | 33,880 | 1,369,728 | 64 | 4 | - | Now |
| EP2SGX60D | 8 | 60,440 | 2,544,192 | 144 | 4 | - | Now |
| EP2SGX60E | 12 | 60,440 | 2,544,192 | 144 | 8 | - | Now |
| EP2SGX90E | 12 | 90,960 | 4,520,448 | 192 | 8 | Now | Now |
| EP2SGX90F | 16 | 90,960 | 4,520,448 | 192 | 8 | Now | Now |
| EP2SGX130G | 20 | 132,540 | 6,747,840 | 252 | 8 | Now | Now |
- Each Stratix II GX digital signal processing (DSP) block can implement four 18x18 multipliers or one 36x36 multiplier. To obtain the total number of 36x36 multipliers per device, divide the total number of 18x18 multipliers by a factor of 4
- Includes both enhanced and fast phase-locked loops (PLLs)
- Planned dates are subject to change
