With the inclusion of dynamic phase alignment (DPA) circuitry, Stratix® II devices offer enhanced support for source-synchronous protocols. The enhanced source-synchronous channels on Stratix II devices support 1.040-Gbps data transfer, while the dedicated DPA circuitry simplifies printed circuit board (PCB) design by eliminating signal-alignment issues introduced by clock-to-channel and channel-to-channel skew. Stratix II devices support a wide array of high-speed protocols, including the SPI-4.2, SFI-4, XSBI, RapidIO™, HyperTransport™, Network Processing Forum (NPF) Streaming Interface (SI) or NPSI, and UTOPIA IV standards (as shown in Figure 1 and Table 1).
Designers can use Altera® intellectual property (IP) cores to bridge high-speed interfaces through the Atlantic™ interface. Stratix II devices can also support several high-bandwidth interfaces at once in one device for an unparalleled bridging solution.
Figure 1. Stratix II Support for Various High-Speed Protocol Interfaces
Note to Figure 1:
- ASSP = Application-specific standard product
| Table 1: Standard Interfaces Supported in Stratix II Devices | |||||||
| Features | SPI-4.2 | SFI-4 | XSBI | RapidIO | HyperTransport | NPSI | Utopia IV |
|---|---|---|---|---|---|---|---|
| Protocol Bandwidth (Gbps) | 10 | 10 | 10 | 10 | 6.4 | 16 | 10 |
| Data (Bus Width) | 16 | 16 | 16 | 8, 16 | 8, 16 | 16 | 8, 16, 32 |
| Control or Frame | 1 | 0 | 0 | 1 | 1,2 | 5 | 1 |
| Total Tx Channels Available |
21 | 17 | 17 | 10, 19 | 10, 19 | 23 | 10, 18, 34 |
| Total Rx Channels Available |
19 | 16 | 16 | 9, 17 | 9, 17 | 21 | 9, 17, 33 |
| Clocks | 1 | 1 | 1 | 1, 2 | 1, 2 | 1 | 1 |
| Maximum Data Rate (Mbps) | 1,000 | 622.08 | 644.53 | 1,000 | 1,000 | 1,000 | 415 |
| Maximum Clock Rate (MHz) | 622 | 622.08 | 644.53 | 500 | 500 | 500 | 415 |
| Electrical Standard | LVDS | LVDS | LVDS | LVDS | HyperTransport | LVDS | LVDS |
SPI-4.2
Used in 10-Gbps systems, including OC-192 SONET/SDH and 10-Gigabit Ethernet applications, and becoming a standard chip-to-chip interface, the SPI-4.2 standard interface’s cell and packet transfers at 10-Gbps between physical (PHY) and link layer devices. Stratix II device DPA circuitry eliminates clock-to-channel and channel-to-channel skew requirements by continuously aligning a sampling clock with the incoming data. Features such as TriMatrix™ memory, advanced phase-locked loop (PLL) technology, and double-data rate (DDR) I/O capabilities, combined with the Stratix II family's advanced differential I/O capabilities, deliver a 1-Gbps SPI-4.2 solution. More details on DPA are available on the Stratix II Source-Synchronous Signaling page.
SFI-4
SFI-4 is an Optical Internetworking Forum (OIF) standard used in an OC-192 SONET system to link the framer and the serializer/deserializer (SERDES). Stratix II devices support the required data rates of 622.08 Mbps, along with the required 1:1 relationship between clock frequency and data rate. The Stratix II differential I/O PLL was designed to support these high clock frequencies. Higher data rates are also supported to accommodate system overhead. Stratix II SFI-4 support extends the reach of high-density programmable logic from the backplane to physical layer devices, providing designers with a system-on-a-programmable-chip (SOPC) solution.
XSBI
Based on the SFI-4 standard, the 10 Gigabit Ethernet XSBI protocol is a 16-bit LVDS interface used to connect the physical coding sublayer and physical medium attachment (PMA) sublayers that are common to a family of 10-Gbps physical layer implementations, collectively known as 10GBASE-R. Stratix II devices support the required data rates of up to 644.53 Mbps, along with the required 1:1 relationship between clock frequency and data rate. The Stratix II differential I/O PLL was designed to support the high clock frequencies required for this 1:1 relationship.
RapidIO
The RapidIO interconnect architecture was designed to link network processors, digital signal processing (DSP) devices, and other peripheral devices. It is a high-performance, packet-switched interconnect technology that can exceed 10-Gbps throughput by the use of LVDS links. Stratix II devices support the 500-MHz clock frequency and 1 Gbps data rate required to implement the RapidIO standard. TriMatrix memory, the Stratix II family's leading-edge embedded memory resource, makes implementing the buffering requirements for a RapidIO system in Stratix II devices easy.
HyperTransport
HyperTransport technology is a high-speed, high-performance, point-to-point link technology primarily used as a processor interface. Stratix II differential I/O buffers have been designed to support the specific requirements of the physical layer of HyperTransport technology, including the requirements for a center-aligned clock (with respect to the transferred data) and DDR I/O signaling.
NPSI
The Network Processor Forum defined interfaces from the transfer of traffic between a pair of network processing devices including physical (PHY) layer devices (such as framers, mappers, MACs), network processors, network co-processors and switch fabrics at OC-192 rates. The streaming interface co-exists with the look-aside interface, which is a processor/co-processor to memory interface. Stratix II devices are compatible with the NPSI interface.
Related Links
- Souce-Synchronous Signaling I/O Standards in Stratix II Devices
- Single-Ended I/O Standards in Stratix II Devices
- Using Selectable I/O Standards in Stratix II Devices chapter of the Stratix II Device Handbook
- High-Speed Differential I/O Interfaces With DPA in Stratix II Devices chapter of the Stratix II Device Handbook
